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CS47L24 Datasheet(PDF) 11 Page - Cirrus Logic |
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CS47L24 Datasheet(HTML) 11 Page - Cirrus Logic |
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11 / 256 page ![]() CS47L24 Rev 4.1 11 RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN TYP MAX UNIT Digital supply range (Core) See note 2 DCVDD 1.14 1.2 1.26 V Digital supply range (I/O) DBVDD 1.71 1.8 2.75 V Charge Pump supply range CPVDD 1.71 1.8 1.89 V Analogue supply range See note 2 AVDD 1.71 1.8 1.89 V Microphone Bias supply MICVDD 1.71 3.6 V Speaker supply range SPKVDD 2.4 5.5 V Ground See note 1 DGND, AGND, CPGND, SPKGNDN, SPKGNDP, SUBGND 0 V Power supply rise time See notes 3, 4, 5 DCVDD 10 2000 µs All other supplies 10 Operating temperature range TA -40 85 °C Notes: 1. The impedance between DGND, AGND, CPGND and SUBGND should be less than 0.1 Ω.The impedance between SPKGND and SUBGND should be less than 0.2 Ω. 2. AVDD must be supplied before or simultaneously to DCVDD. DCVDD must not be powered if AVDD is not present. There are no other power sequencing requirements. 3. If the DCVDD rise time exceeds 2ms, then RESET ¯¯¯¯¯¯ must be asserted (low) during the rise, and held asserted until after DCVDD is within the recommended operating limits. 4. The specified minimum power supply rise times assume a minimum decoupling capacitance of 100nF per pin. However, Cirrus Logic strongly advises that the recommended decoupling capacitors are present on the PCB and that appropriate layout guidelines are observed. 5. The specified minimum power supply rise times also assume a maximum PCB inductance of 10nH between decoupling capacitor and pin. |
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