CS47L24 datasheet(56/256 Pages) CIRRUS

56 / 256 page

CS47L24

Rev 4.1

to trigger other events. The Signal Detect function can be used as an Interrupt event, or as a GPIO output, or used to

trigger the Control Write Sequencer (note - DRC1 only).

DRCnLMIX_VOL2

DRCnLMIX_VOL3

DRCnLMIX_VOL4

DRCnLMIX_VOL1

DRCnLMIX_SRC1

DRCnLMIX_SRC3

DRCnLMIX_SRC4

DRCnLMIX_SRC2

DRC1 Left (58h)

DRC2 Left (5Ah)

DRC

Dynamic Range Controller

DRCnRMIX_VOL2

DRCnRMIX_VOL3

DRCnRMIX_VOL4

DRCnRMIX_VOL1

DRCnRMIX_SRC1

DRCnRMIX_SRC3

DRCnRMIX_SRC4

DRCnRMIX_SRC2

DRC1 Right (59h)

DRC2 Right (5Bh)

DRC

Dynamic Range Controller

CS47L24 supports 2 Stereo DRC blocks, ie. n = 1 or 2

Figure 18 Dynamic Range Control (DRC) Block

The DRC1 and DRC2 mixer control registers (see Figure 18) are located at register addresses R2240 (8C0h) through to

R2271 (08DFh).

The full list of digital mixer control registers is provided in the “Register Map” section (Register R1600 through to R3000).

Generic register definitions are provided in Table 7.

The *_SRCn registers select the input source(s) for the respective DRC processing blocks. Note that the selected input

source(s) must be configured for the same sample rate as the DRC to which they are connected. Sample rate conversion

functions are available to support flexible interconnectivity -

see “Asynchronous Sample Rate Converter (ASRC)” and

“Isochronous Sample Rate Converter (ISRC)”.

The bracketed numbers in Figure 18,

e.g.,”(58h)” indicate the corresponding *_SRCn register setting for selection of that

signal as an input to another digital core function.

The sample rate for the DRC function is configured using the FX_RATE register - see Table 21. Note that the EQ, DRC

and LHPF functions must all be configured for the same sample rate.

The DRC function supports audio sample rates in the range 8kHz to 96kHz. Higher sample rates (up to 192kHz) may be

selected using FX_RATE, provided that the DRC function is disabled.

Sample rate conversion is required when routing the DRC signal paths to any signal chain that is asynchronous and/or

configured for a different sample rate.

The DRC functions are enabled using the control registers described in Table 11.

CS47L24 Datasheet(PDF) 56 Page - Cirrus Logic

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