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CS47L24 Datasheet(PDF) 29 Page - Cirrus Logic |
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CS47L24 Datasheet(HTML) 29 Page - Cirrus Logic |
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29 / 256 page  CS47L24 Rev 4.1 29 JTAG INTERFACE TIMING TCK (input) tCCH tCCL tCCY TDI (input) tDSU tDH TMS (input) tMSU tMH TDO (output) tDD TRST (input) tRSU tRH Figure 8 JTAG Interface Timing Test Conditions The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted. CLOAD = 25pF (output pins). TCK slew (20% to 80%) = 5ns. PARAMETER SYMBOL MIN TYP MAX UNIT JTAG Interface Timing TCK cycle time TCCY 50 ns TCK pulse width high TCCH 20 ns TCK pulse width low TCCL 20 ns TMS setup time to TCK rising edge TMSU 1 ns TMS hold time from TCK rising edge TMH 2 ns TDI setup time to TCK rising edge TDSU 1 ns TDI hold time from TCK rising edge TDH 2 ns TDO propagation delay from TCK falling edge TDD 0 17 ns TRST setup time to TCK rising edge TRSU 3 ns TRST hold time from TCK rising edge TRH 3 ns TRST pulse width low 20 ns |
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