CS47L24 datasheet(36/256 Pages) CIRRUS

36 / 256 page

CS47L24

Rev 4.1

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

IN1R_ENA

Input Path 1 (Right) Enable

0 = Disabled

1 = Enabled

R769

(0301h)

Input

Enables

Status

IN2L_ENA_STS

Input Path 2 (Left) Enable Status

0 = Disabled

1 = Enabled

IN2R_ENA_STS

Input Path 2 (Right) Enable Status

0 = Disabled

1 = Enabled

IN1L_ENA_STS

Input Path 1 (Left) Enable Status

0 = Disabled

1 = Enabled

IN1R_ENA_STS

Input Path 1 (Right) Enable Status

0 = Disabled

1 = Enabled

Table 2 Input Signal Path Enable

INPUT SIGNAL PATH SAMPLE RATE CONTROL

The input signal paths may be selected as input to the digital mixers or signal processing functions within the CS47L24

digital core. The sample rate for the input signal paths is configured using the IN_RATE register - see Table 21 within the

“Digital Core” section.

Note that sample rate conversion is required when routing the input signal paths to any signal chain that is asynchronous

and/or configured for a different sample rate.

INPUT SIGNAL PATH CONFIGURATION

A configurable high pass filter (HPF) is provided on the left and right channels of each input path. The applicable cut-off

frequency is selected using the IN_HPF_CUT register. The filter can be enabled on each path independently using the

INnx_HPF bits.

The voltage reference for the digital microphone input/output pins is selectable using the INn_DMIC_SUP registers -

each interface may be referenced to MICVDD, or to the MICBIAS1 or MICBIAS2 levels.

The DMICCLKn frequency for each stereo input path can be configured using the INn_OSR register bits.

A digital delay may be applied to any of the digital microphone input channels. This feature can be used for phase

adjustment of any digital input, including directional control of multiple microphones. The delay is controlled using the

INnL_DMIC_DLY and INnR_DMIC_DLY registers.

The input signal paths are configured using the register bits described in Table 3.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R780

(030Ch)

HPF

Control

2:0

IN_HPF_CUT

[2:0]

010

Input Path HPF Select

Controls the cut-off frequency of the input

path HPF circuits.

000 = 2.5Hz

001 = 5Hz

010 = 10Hz

011 = 20Hz

100 = 40Hz

All other codes are Reserved

R784

(0310h)

IN1L

IN1L_HPF

Input Path 1 (Left) HPF Enable

0 = Disabled

1 = Enabled

CS47L24 Datasheet(PDF) 36 Page - Cirrus Logic

CS47L24 Datasheet(HTML) 36 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL