VR4102 datasheet(195/701 Pages) NEC

195 / 701 page

CHAPTER 6 EXCEPTION PROCESSING

195

Figure 6-15. TLB/XTLB Refill Exception Handler (2/2)

(b) Guideline of TLB/XTLB exception handler (software)

Execute MFC0 instruction

X/Context register

ERET

Servicing by each exceoption routine

Guideline of TLB/XTLB exception handler

; The occurence of TLB Mismatch, TLB Invalid, and TLB Modified

exception is disabled by using an unmapped space.

; The occurence of the Watch and Interrupt exceptions is disabled by

setting EXL = 1.

; Other exceptions are avoided in the OS programs.

; However, the Cache error, Cold reset, Soft reset, and NMI exceptions

are enabled.

; The physical address for a virtual address loaded into the X/Context

; As long as a data/instruction address exists in the mapping space,

another TLB Mismatch exception may occur. In such a case, EXL = 1 is

set, causing a jump to the common exception vector. (In this case, the

common exception handler handles the TLB miss or the ERET instruction

returns control to the user program, then a TLB Mismatch exception is

generated again.)

; The execution of the ERET instruction is disabled in the branch delay

slots of other jump instructions.

; The processor does not execute an instruction in the branch delay slot

of the ERET instruction.

; PC

← EPC, EXL ← 0

VR4102 Datasheet(PDF) 195 Page - NEC