VR4102 datasheet(199/701 Pages) NEC

199 / 701 page

199

CHAPTER 7 INITIALIZATION INTERFACE

This chapter describes the initialization interface and processor modes.

It also explains the reset signal

descriptions and types, signal- and timing-related dependence, and the initialization sequence during each mode

that can be selected by the user.

Remark

# that follows signal names indicates active low.

7.1 RESET FUNCTION

There are five ways to reset the VR4102. Each is summarized below.

7.1.1 RTC Reset

During power-on, set the RTCRST# pin as active. After waiting (about 600 ms) for the 32.768-kHz oscillator to

begin oscillating when the power supply is stable at 3.0 V or above, setting the RTCRST# pin as inactive causes the

RTC unit to begin counting. Next, when the POWER pin, DCD# pin, or GPIO[3] pin becomes inactive, the VR4102

asserts the POWERON pin and uses the BATTINH/BATTINT# signal to perform a battery level check. If the battery

check’s result is OK, the VR4102 asserts the MPOWER pin and waits for the stabilization time period (about 350 ms)

for the external agent’s DC/DC converter, then begins PLL oscillation and starts all clocks (a period of about 16 ms

following the start of PLL oscillation is required for stabilization of PLL oscillation).

An RTC reset does not save any of the status information and it completely initializes the processor’s internal

state. Since the DRAM is not switched to self refresh mode, the contents of DRAM after an RTC reset are not at all

guaranteed.

After a reset, the processor becomes the system bus master and it begins the Cold reset exception sequence to

access the reset vectors in the ROM space. Since only part of the internal status is reset when a reset occurs in the

VR4102, the processor should be completely initialized by software.

VR4102 Datasheet(PDF) 199 Page - NEC