VR4102 datasheet(196/701 Pages) NEC

196 / 701 page

CHAPTER 6 EXCEPTION PROCESSING

196

Figure 6-16. Cache Error Exception Handler

The Cache Error exception can be masked by setting the DE (SR16) bit to 1. When ERL = 1, Cache

Error exceptions are masked.

Instruction

in branch delay

slot?

Set cache

error register

Yes

BD bit

← 1

Error EPC

← PC – 4

BD bit

← 0

Error EPC

← PC

BEV

(SR22)

← 0xFFFF FFFF A000 0000 + 100

(Unmapped, uncached space)

= 0 (normal)

= 1 (bootstrap)

ERL

← 1

Servicing by exception routine

ERET

Remark

← 0xFFFF FFFF BFC0 0200 + 100

(Unmapped, uncached space)

Start

Hardware

Software

Yes

ERL = 1?

(SR2)

; Check for multple exceptions

; The execution of the ERET instruction is disabled in the branch delay

slots of other jump instructions.

; The processor does not execute an instruction in the branch delay slot

of the ERET instruction.

; PC

← Error EPC, ERL ← 0

; The Cache Error and TLB-related Error exceptions do not occur because

of unmapped/uncache vector.

; The occurence of the Watch and Interrupt exceptions is disabled by

setting ERL = 1.

; Other exceptions are avoided in the OS programs.

; However, the Cold reset, Soft reset, and NMI exceptions are enabled.

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