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VR4102 Datasheet(PDF) 245 Page - NEC |
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VR4102 Datasheet(HTML) 245 Page - NEC |
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245 / 701 page ![]() CHAPTER 10 BCU (BUS CONTROL UNIT) 245 10.2.8 CLKSPEEDREG (0x0B00 0014) Bit D15 D14 D13 D12 D11 D10 D9 D8 Name DIV2B Reserved Reserved Reserved Reserved Reserved Reserved Reserved R/W R RR RRR R R RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit D7D6D5 D4D3 D2D1 D0 Name Reserved Reserved Reserved CLKSP[4] CLKSP[3] CLKSP[2] CLKSP[1] CLKSP[0] R/W RRR RR RR R RTCRST 0 0 0 Undefined Undefined Undefined Undefined Undefined Other resets 0 0 0 Undefined Undefined Undefined Undefined Undefined Bit Name Function D[15] DIV2B The multiplier of TClock frequency. This bit always indicates 0 in the current VR4102. 1: Reserved 0: Multiplied by 16 D[14..5] Reserved Write 0 when writing. 0 is returned after a read. D[4..0] CLKSP[4..0] These bits indicate the value used to calculate the frequency of PClock and TClock. This register is used to indicate the value to calculate the frequencies of the peripheral unit’s operating clock (TClock) and CPU core’s operating clock (PClock). The PClock frequency obtained from this register’s setting is the same as the frequency selected by setting CLKSEL[2:0] pins. The following method is used to calculate TClock frequency. TClock = (18.432 MHz/CLKSP[4..0])*16 The following method is used to calculate PClock frequency. PClock = (18.432 MHz/CLKSP[4..0])*32 |
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