VR4102 datasheet(247/701 Pages) NEC

247 / 701 page

CHAPTER 10 BCU (BUS CONTROL UNIT)

247

10.4 NOTES ON USING BCU

10.4.1 CPU Core Bus Modes

The VR4102 is designed on the assumption that the CPU core is set to the following mode.

• Writeback data rate

: D

• Accelerate data ratio : VR4x00 compatible mode

Therefore, set the Config Register as below:

•

EP : 0000

•AD : 0

10.4.2 Access Data Size

In the VR4102, access size is restricted for each address space. Access sizes for the following address spaces

are listed below.

Table 10-4. Access Size Restrictions for Address Spaces

Address space

R/W

Access size (bytes)

Remark

321

ROM/PageROM

{{{

Flash memory

Note 1

System bus I/O space

R/W

{{{

{{

System bus memory space

R/W

{{{

{{

On-chip I/O space 1

R/W

{{{

{{

On-chip I/O space 2

R/W

{{

{

LCD space

R/W

{{

Notes 2, 3

High-speed system bus memory space

R/W

{{

Note 3

DRAM

R/W

{{{

Notes 1.

The access size when writing to flash memory must be the same as the data bus width such as below;

In 32-bit mode: 4 bytes

In 16-bit mode: 2 bytes

Use as uncached.

The LCD space and high-speed system bus memory space are mapped to the same physical

address.

Use BCUCNTREG1’s ISAM/LCD bit to switch between the two.

Remark

: accessible,

u : not accessible

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