VR4102 datasheet(246/701 Pages) NEC

246 / 701 page

CHAPTER 10 BCU (BUS CONTROL UNIT)

246

10.3 CONNECTION OF ADDRESS PINS

Physical address output from the CPU core is provided to external devices through ADD bus.

The

correspondence between the address output to ADD bus and the address bits of external devices differs depending

on the external devices as shown in Table 10-2. Therefore, connect ADD bus and address pin of the external device

as shown in Table 10-3.

Table 10-2. Address Bit Correspondence between ADD Bus and External Devices

ADD bus

Devices connected

1011 1213 1415 161718 1920 212223 24 25

ROM, LCD, ISA,

DRAM (ROW)

1011 1213 1415 161718 1920 212223 24 25

DRAM (COLUMN),

DATA [15:0]

456

123

19 20 19 20 21 22 23 24 25

DRAM (COLUMN),

DATA [31:0]

456

19 20 19 20 21 22 23 24 25

Table 10-3. Address Connection Table with External Devices

Address bits of external devices

VR4102 pin

16M-bit DRAM

64M-bit DRAM,

DATA[15..0]

64M-bit DRAM,

DATA[31..0]

ADD[9]

ADD[10]

ADD[11]

ADD[12]

ADD[13]

ADD[14]

ADD[15]

ADD[16]

ADD[17]

ADD[18]

ADD[19]

A10/NC

Note 1

ADD[20]

A11/NC

Note 1

A12/NC

Note 2

A12/NC

Note 3

ADD[21]

A10

ADD[22]

A11

A10

ADD[23]

A11

Notes 1. A10, A11 :

PPD42S16165, NC : PPD42S18165

2. A12 :

PPD42S64165, NC : PPD42S65165

3. A12 :

PPD42S64165, NC : PPD42S65165

VR4102 Datasheet(PDF) 246 Page - NEC

VR4102 Datasheet(HTML) 246 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL