| Electronic Components Datasheet Search |
|
VR4102 Datasheet(PDF) 411 Page - NEC |
|
|
|||||||||||||||||||||||||||||
VR4102 Datasheet(HTML) 411 Page - NEC |
|
411 / 701 page ![]() CHAPTER 20 AIU (AUDIO INTERFACE UNIT) 411 20.2.2 SDMADATREG (0x0B00 0162) Bit D15 D14 D13 D12 D11 D10 D9 D8 Name Reserved Reserved Reserved Reserved Reserved Reserved SDMA[9] SDMA[8] R/W R RR RRR R/W R/W RTCRST 00 00 0 0 1 0 Other resets 0 0 0 0 0 0 1 0 Bit D7 D6D5 D4D3D2 D1 D0 Name SDMA[7] SDMA[6] SDMA[5] SDMA[4] SDMA[3] SDMA[2] SDMA[1] SDMA[0] R/W R/W R/W R/W R/W R/W R/W R/W R/W RTCRST 00 00 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function D[15:10] Reserved Write 0 when writing. 0 is returned after a read. D[9:0] SDMA[9:0] Speaker output DMA data (from buffer to SODATREG) This register is used to store 10-bit DMA data for speaker output. When SODATREG is empty, the data is transferred to SODATREG. Write is used for debugging and is enabled when AIUSEN bit of SEQREG is set to 1. This register is cleared (0x0200) by resetting AIUSEN bit of SEQREG to 0. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |