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VR4102 Datasheet(PDF) 416 Page - NEC

Part # VR4102
Description  64/32-bit Microprocessor
PDF  701 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

VR4102 Datasheet(HTML) 416 Page - NEC

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CHAPTER 20 AIU (AUDIO INTERFACE UNIT)
416
20.2.7 MCNTREG (0x0B00 0172)
Bit
D15
D14
D13
D12
D11
D10
D9
D8
Name
ADENAIU
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/W
R/W
RR
RRR
R
R
RTCRST
0
0
0
0
0
0
0
0
Other resets
0
0
0
0
0
0
0
0
Bit
D7
D6D5
D4D3D2
D1
D0
Name
Reserved
Reserved
Reserved
Reserved
MSTATE
Reserved
MSTOPEN
ADREQAIU
R/W
R
RR
RRR
R/W
R
RTCRST
0
0
0
0
0
0
0
0
Other resets
0
0
0
0
0
0
0
0
Bit
Name
Function
D[15]
ADENAIU
This is the MIC A/D enable bit. It controls the ON/OFF status of the Vref input to the
D/A converter’s ladder resistors in the A/D converter.
1 : Vref ON
0 : Vref OFF
D[14:4]
Reserved
Write 0 when writing. 0 is returned after a read.
D[3]
MSTATE
Indicates MIC operation state (= AIUMEN)
1 : In operation
0 : Stopped
D[2]
Reserved
Write 0 when writing. 0 is returned after a read.
D[1]
MSTOPEN
MIC input DMA transfer 1-page boundary interrupt stop
1 : Stop DMA request at 1-page boundary
0 : Stop DMA request at 2-page boundary
D[0]
ADREQAIU
A/D use request bit
1 : Request
0 : Normal
This register is used to control the AIU’s MIC block.
ADENAIU bit controls the connection of AVDD and Vref input to ladder type resistors in the A/D converter. Setting
this bit to 0 (OFF) allows low power consumption when not using the A/D converter. When using A/D converter, this
bit must be set following the sequence described in 20.3.
The contents of MSTATE bit is valid only when AIUMEN bit of SEQREG is set to 1.
This unit has priority when a conflict occurs with the PIU in relation to A/D requests.



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