VR4102 datasheet(451/701 Pages) NEC

451 / 701 page

CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT)

451

22.3.3 Reception

Once reception enable has been set, sampling of the DDIN pin begins and, when a start bit is detected, data

reception begins. A receive complete interrupt (Dsiu_Intst0) occurs each time reception of one frame of data is

completed. Normally, this interrupt service is used to transfer receive data from a receive buffer (RXB0REG or

RXB0LREG) to memory.

Reception enable status

Setting the ASIM00REG’s bit[6] sets enable status for the receive operation, and a zero is output to DRTS#.

RXE0 = 1: Reception enable status

DRTS# = 0

RXE0 = 0: Reception prohibit status

DRTS# = 1

The reception hardware is initialized and enters idle mode when reception prohibit status has been set. Once

that happens, receive complete interrupts and receive error interrupts are not issued and the contents of the

receive buffer are retained.

Activation of receive operation

The receive operation is activated when a start bit is detected.

The DDIN pin is sampled at the interval set by the serial clock specified via the ASIM00REG. Once a signal’s

falling edge is detected at the DDIN pin, the DDIN pin is again sampled after an interval of eight serial clocks.

This time, when a low-level state is detected it is recognized as a start bit and control is passed to the receive

operation, after which the DDIN pin continues to be sampled using an interval of 16 serial clocks.

After eight serial clocks have elapsed since a signal’s falling edge was detected at the DDIN pin, when

sampling recognizes a high-level state it does not recognize the signal’s falling edge as a start bit. Instead,

the serial clock counter used for the sampling timing is initialized and the receive operation is halted until the

next edge input.

Receive complete interrupt request

When RXE0 = 1 and one frame of data has been received, the receive data in the shift register is transferred

to RXB0REG and a receive complete interrupt request (Dsiu_Intsr0) is issued.

Even when an error has

occurred, the receive data for which the error occurred is still transferred to a receive buffer (RXB0REG or

RXB0LREG) and two interrupts; a receive complete interrupt (Dsiu_Intsr0) and a receive error interrupt

(Dsiu_Intser0), occur at the same time.

If the RXE0 bit is reset (to “0”) during a receive operation, the receive operation is halted immediately. At that

point, the contents of the receive buffer (RXB0REG or RXB0LREG) and ASIS0REG are not changed and

neither the receive complete interrupt (Dsiu_Intsr0) nor the receive error interrupt (Dsiu_Intser0) occur.

Figure 22-3. Receive Complete Interrupt Timing

Dsiu_Intsr0

Parity

Start

Stop

DDIN

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