| Electronic Components Datasheet Search |
|
VR4102 Datasheet(PDF) 476 Page - NEC |
|
|
|||||||||||||||||||||||||||||
VR4102 Datasheet(HTML) 476 Page - NEC |
|
476 / 701 page ![]() CHAPTER 24 SIU (SERIAL INTERFACE UNIT) 476 24.2.11 SIUMS (0x0C00 0006) Bit D7 D6D5 D4D3D2 D1 D0 Name MSR[7] MSR[6] MSR[5] MSR[4] MSR[3] MSR[2] MSR[1] MSR[0] R/W R R R R R/W R/W R/W R/W RTCRST Undefined Undefined Undefined Undefined 0 0 0 0 Other resets Undefined Undefined Undefined Undefined 0 0 0 0 Bit Name Function D[7] MSR[7] Complement of DCD# signal 1 : High level 0 : Low level D[6] MSR[6] Complement of RI signal (internal) 1 : High level 0 : Low level D[5] MSR[5] Complement of DSR# input 1 : High level 0 : Low level D[4] MSR[4] Complement of CTS# input 1 : High level 0 : Low level D[3] MSR[3] DCD# signal change 1 : Change in DCD# signal 0 : No change D[2] MSR[2] RI signal (internal) change 1 : Change in RI signal (internal) 0 : No change D[1] MSR[1] DSR# signal change 1 : Change in DSR# signal 0 : No change D[0] MSR[0] CTS# signal change 1 : Change in CTS# signal 0 : No change This register indicates the current status of various control signals that are input to the CPU from a modem or other peripheral device. MSR[3..0] bits are cleared to 0 when they are read. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |