VR4102 datasheet(474/701 Pages) NEC

474 / 701 page

CHAPTER 24 SIU (SERIAL INTERFACE UNIT)

474

24.2.10 SIULS (0x0C00 0005)

Bit

D6D5

D4D3D2

Name

LSR[7]

LSR[6]

LSR[5]

LSR[4]

LSR[3]

LSR[2]

LSR[1]

LSR[0]

R/W

RTCRST

Other resets

Bit

Name

Function

D[7]

LSR[7]

Indicates error detection (in FIFO mode)

1 : Parity error, framing error, or break is detected

0 : Normal

D[6]

LSR[6]

Transmit block empty

1 : No data in transmit holding register or transmit shift register

No data in transmit FIFO (during FIFO mode)

0 : Data exists in transmit holding register or transmit shift register

Data exists in transmit FIFO (during FIFO mode)

D[5]

LSR[5]

Transmit holding register empty

1 : Character is transferred to transmit shift register (during 16550 mode)

Transmit FIFO is empty (during FIFO mode)

0 : Character is stored in transmit holding register (during 16550 mode)

Transmit data exists in transmit FIFO (during FIFO mode)

D[4]

LSR[4]

Break interrupt

1 : Break interrupt detected

0 : Normal

D[3]

LSR[3]

Framing error

1 : Framing error detected

0 : Normal

D[2]

LSR[2]

Parity error

1 : Parity error detected

0 : Normal

D[1]

LSR[1]

Overrun error

1 : Overwrite receive data

0 : Normal

D[0]

LSR[0]

Receive data ready

1 : Receive data exists in FIFO

0 : No receive data in FIFO

The CPU uses this register to get information related to data transfers.

LSR[7] bit is valid only in FIFO mode, and it indicates always 0 in 16550 mode.

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