VR4102 datasheet(471/701 Pages) NEC

471 / 701 page

CHAPTER 24 SIU (SERIAL INTERFACE UNIT)

471

When transmit FIFO is use-enabled and transmit interrupts are enabled, transmit interrupts can occur as

described below.

When the transmit FIFO becomes empty, a transmit holding register empty interrupt occurs.

This interrupt is cleared when a character is written to the transmit holding register (from one to 16

characters can be written to the transmit FIFO during servicing of this interrupt), or when the SIUIID

(interrupt ID register) is read.

If there are not at least two bytes of character data in the transmit FIFO between one time when LSR[5] = 1

(transmit FIFO is empty) and the next time when LSR[5] = 1, empty transmit FIFO status is reported to the

IIR after a delay period calculated as “the time for one character

ð the time for the last stop bit(s).”

When transmit interrupts are enabled, the first transmit interrupt that occurs after the FCR0 (FIFO enable bit)

is overwritten is indicated immediately.

The priority level of the character timeout interrupt and receive FIFO trigger level interrupt is the same as that of

the receive data ready interrupt.

The priority level of the transmit FIFO empty interrupt is the same as that of the transmit holding register empty

interrupt.

z FIFO polling mode

When FCR0 = 1 (FIFO is enabled), if the value of any or all of the interrupt enable register (SIUIE) bits 3 to 0

becomes “0”, the SIU enters FIFO polling mode. Because the transmit block and receive block are controlled

separately, polling mode can be set for either or both blocks.

When in this mode, the status of the transmit block and/or receive block can be checked by reading the line

status register (SIULS) via a user program.

When in FIFO polling mode, there is no notification when the trigger level is reached or when a timeout occurs,

but the receive FIFO and transmit FIFO can still store characters as they normally do.

VR4102 Datasheet(PDF) 471 Page - NEC