VR4102 datasheet(470/701 Pages) NEC

470 / 701 page

CHAPTER 24 SIU (SERIAL INTERFACE UNIT)

470

z FIFO interrupt modes

When receive FIFO is enabled and receive interrupts are enabled, receive interrupts can occur as described

below.

When the FIFO is reached to the specified trigger level, a receive data ready interrupt occurs to inform the

CPU.

This interrupt is cleared when the FIFO goes below the trigger level.

When the FIFO is reached to the specified trigger level, the SIUIID register indicates a receive data ready

interrupt.

As with the interrupt above, this interrupt is cleared when the FIFO goes below the trigger level.

Receive line status interrupts are assigned a higher priority level than are receive data ready interrupts.

When characters are transferred from the shift register to the receive FIFO, “1” is set to the LSR0 bit.

The value of this bit returns to “0” when the FIFO becomes empty.

When receive FIFO is use-enabled and receive interrupts are enabled, receive FIFO timeout interrupts can

occur as described below.

The following are conditions under which FIFO timeout interrupts occur.

• At least one character is being stored in the FIFO.

• The time required for sending four characters has elapsed since the serial reception of the last character

(includes the time for two stop bits in cases where a stop bit has been specified).

• The time required for sending four characters has elapsed since the CPU last accessed the FIFO.

The time between receiving the last character and issuing a timeout interrupt is a maximum of 160 ms

when operating at 300 baud and receiving 12-bit data.

The transfer time for a character is calculated based on the baud rate clock for reception (internal) input as

clock signals (which is why the elapsed time is in proportion to the baud rate).

Once a timeout interrupt has occurred, the timeout interrupt is cleared and the timer is reset as soon as the

CPU reads one character from the receive FIFO.

If no timeout interrupt has occurred, the timer is reset when a new character is received or when the CPU

reads the receive FIFO.

VR4102 Datasheet(PDF) 470 Page - NEC