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VR4102 Datasheet(PDF) 500 Page - NEC

Part # VR4102
Description  64/32-bit Microprocessor
PDF  701 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

VR4102 Datasheet(HTML) 500 Page - NEC

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CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT)
500
26.2.2 DPINTR (0x0C00 0042)
Bit
D15
D14
D13
D12
D11
D10
D9
D8
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/W
RRR
RR
RR
R
RTCRST
000
00
00
0
Other resets
0
0
0
0
0
0
0
0
Bit
D7D6D5
D4D3
D2D1
D0
Name
Reserved
Reserved
Reserved
FDPINT5
FDPINT4
FDPINT3
FDPINT2
FDPINT1
R/W
R
R
R
R
R/W
R/W
R/W
R/W
RTCRST
000
00
00
0
Other resets
0
0
0
0
0
0
0
0
Bit
Name
Function
D15 to D5
Reserved
Write 0 when writing. 0 is returned after a read.
D4
FDPINT5
This bit indicates an FIR macro interrupt occurs. Cleared to 0 when 1 is written.
0: Normal
1: Occurred
D3
FDPINT4
This bit indicates that the DMA buffer (receive side) becomes full (2 pages).
Cleared to 0 when 1 is written.
0: Normal
1: Occurred (DMA request is stopped)
Caution The last data of the transfer data is not guaranteed.
D2
FDPINT3
This bit indicates that the DMA buffer (transmit side) becomes full (2 pages).
Cleared to 0 when 1 is written.
0: Normal
1: Occurred (DMA request is stopped)
Caution The last data of the transfer data is not guaranteed.
D1
FDPINT2
This bit indicates that the DMA buffer (receive side) becomes full (1 page).
Cleared to 0 when 1 is written.
0: Normal
1: Occurred (when bit 0 of DPCNTR is 1, DMA request is stopped)
Caution When 1-page transfer is set, the last data of the transfer data is not
guaranteed.
D0
FDPINT1
This bit indicates that the DMA buffer (transmit side) becomes full (1 page).
Cleared to 0 when 1 is written.
0: Normal
1: Occurred (when bit 0 of DPCNTR is 1, DMA request is stopped)
Caution When 1-page transfer is set, the last data of the transfer data is not
guaranteed.
This register is used to indicate the generation of FIR’s DMA page interrupt request.



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