VR4102 datasheet(503/701 Pages) NEC

503 / 701 page

CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT)

503

26.2.5 RDR (0x0C00 0052)

Bit

D15

D14

D13

D12

D11

D10

Name

Reserved

R/W

RRR

RTCRST

000

Other resets

Bit

D7D6D5

D4D3

D2D1

Name

RDR7

RDR6

RDR5

RDR4

RDR3

RDR2

RDR1

RDR0

R/W

RRR

RTCRST

000

Other resets

Bit

Name

Function

D15 to D8

Reserved

Write 0 when writing. 0 is returned after a read.

D7 to D0

RDR7 to 0

Receive FIFO

[Function]

This register is used to store the address from which data is read for the receive data store FIFO.

Up to 64- or 32-byte data (determined by bit 3 of FSR) is stored to the receive data store FIFO.

Receive data is used as follows.

(1) Write

During a frame data reception, the sequencer writes the receive data during the data transfer sequence, and the

write pointer is incremented.

If data is written when the unread data in the receive FIFO reaches the maximum volume, the receive overrun

error occurs and the current frame reception is ended.

The write pointer is not incremented.

After the receive FIFO is cleared, if the number of received frames is less than 7 frames, it is possible to

continue frame reception.

To receive 8 or more frames, read all the data and frames that are already received from the receive FIFO, then

clear the receive FIFO and restart reception.

(2) Read

Data is read from the receive data store FIFO while the IrDA is operating.

When a read operation is completed, the read pointer of the receive data store FIFO is incremented. However, it

is not incremented when the receive FIFO is empty.

When the number of read frames reaches the receive frame size, an interrupt occurs and bit 7 of the RXSTS

[Caution]

If data is read when the receive FIFO is empty (read pointer = write pointer), it may contend with the sequencer’s

write operation. This may cause undefined data.

The error generated by read underrun is not reported in this macro.

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