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VR4102 Datasheet(PDF) 505 Page - NEC |
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VR4102 Datasheet(HTML) 505 Page - NEC |
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505 / 701 page  CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 505 26.2.7 FSR (0x0C00 0056) Bit D15 D14 D13 D12 D11 D10 D9 D8 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R/W RRR RR RR R RTCRST 000 00 00 0 Other resets 0 0 0 0 0 0 0 0 Bit D7D6D5 D4D3 D2D1 D0 Name RX_TH1 RX_TH0 TX_TH1 TX_TH0 F_SIZE TXF_CLR RXF_CLR TX_STOP R/W R/W R/W R/W R/W R/W R/W R/W R/W RTCRST 000 00 00 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function D15 to D8 Reserved Write 0 when writing. 0 is returned after a read. D7 and D6 RX_TH1, 0 These bits are used to specify the receive FIFO’s threshold. RX_TH 1, 0 F_SIZE = 0 F_SIZE = 1 00 01 10 11 1 byte 4 bytes 16 bytes 26 bytes 1 byte 8 bytes 32 bytes 48 bytes D5 and D4 TX_TH1, 0 These bits are used to specify the transmit FIFO’s threshold. TX_TH 1, 0 F_SIZE = 0 F_SIZE = 1 00 01 10 11 1 byte 8 bytes 16 bytes 26 bytes 1 byte 16 bytes 32 bytes 48 bytes D3 F_SIZE This bit is used to specify the maximum size of transmit/receive FIFO. F_SIZE FIFO maximum size 0 1 32 bytes 64 bytes D2 TXF_CLR Transmit FIFO clear trigger (read value = 0) When this bit is set to 1, the pointers of the transmit data FIFO and transmit frame size FIFO are initialized. D1 RXF_CLR Receive FIFO clear trigger (read value = 0) When this bit is set to 1, the pointers of the receive data FIFO, receive frame size FIFO, and receive status FIFO are initialized. D0 TX_STOP Transmission stop trigger (read value = 0) When this bit is set to 1, the current frame transmission is stopped and the abort frame transmission starts. The following frames scheduled to be transmitted next are not transferred. Setting 1 to this bit also stops DMA operation and generates the DMA completion interrupt. This register is used to specify the settings for the transmit/receive FIFOs. |
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