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VR4102 Datasheet(PDF) 507 Page - NEC

Part # VR4102
Description  64/32-bit Microprocessor
PDF  701 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

VR4102 Datasheet(HTML) 507 Page - NEC

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CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT)
507
26.2.8 IRSR1 (0x0C00 0058)
Bit
D15
D14
D13
D12
D11
D10
D9
D8
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/W
RRR
RR
RR
R
RTCRST
000
00
00
0
Other resets
0
0
0
0
0
0
0
0
Bit
D7D6D5
D4D3
D2D1
D0
Name
IRDA_EN
Reserved
Reserved
Reserved
Reserved
Reserved
IRDA_MD
MIR_MD
R/W
R/W
RR
RR
R
R/W
R/W
RTCRST
000
00
00
0
Other resets
0
0
0
0
0
0
0
0
Bit
Name
Function
D15 to D8
Reserved
Write 0 when writing. 0 is returned after a read.
D7
IRDA_EN
This bit is used to control (enable/prohibit) IrDA macro operation.
When this bit is set to 1, peripheral main block’s reset is released and clock supply
starts.
0: Prohibit
1: Enable
D6 to D2
Reserved
Write 0 when writing. 0 is returned after a read.
D1 and D0
IRDA_MD/
These bits are used to specify the IrDA/MIR mode.
MIR_MD
IRDA_MD
MIR_MD
Operation mode
Frequency
Modulation
method
0
1
1
1 or 0
0
1
FIR mode
MIR full mode
MIR half mode
8 MHz
1.152MHz
0.576 MHz
4 PPM
Bit stream/stuff
Bit stream/stuff
[Caution]
During transmission/reception, the contents of this register must not be changed (refresh is possible).
When the IRDA_EN bit is set, the peripheral main part reset is released and the clock supply starts.
Pulse output level changes according to operation mode changes.
The operation mode should be changed after changing the IrDA operation to prohibit state (by setting bit (bit 7) to
0).
Once the mode is changed, be sure to switch bit inversion of I/O data ON/OFF by setting bit 0 of the CRCSR
register.
The output level does not change because output latch is reset.
Example) Sequence of changing operation mode from FIR mode to MIR full mode
clr1
0x7, IRSR1
Prohibit IrDA operation
set1
0x1, IRSR1
Change the mode
set1
0x0, CRCSR
Set bit inversion
set1
0x7, IRSR1
Enable IrDA operation



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