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VR4102 Datasheet(PDF) 692 Page - NEC

Part # VR4102
Description  64/32-bit Microprocessor
PDF  701 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

VR4102 Datasheet(HTML) 692 Page - NEC

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APPENDIX A DIFFERENCES BETWEEN VR4102 AND VR4101
692
A.2.12 DSIU
(1) Hardware Flow Control
The VR4102 has two pins for hardware flow control, DCTS# and DRTS#, while the VR4101 has no pins for it.
(2) Supported Interrupts
The VR4102 DSIU supports receive error interrupt, receive completion interrupt, transmit completion interrupt,
and CTS interrupt. The VR4101 DSIU supports receive error interrupt, receive completion interrupt, and transmit
completion interrupt.
(3) Alternative Functions of DSIU Pins
The VR4102 DSIU pins can be used as general-purpose output port, GPIO[47..44], when DSIU is disabled.
Those of the VR4101 have no alternative functions.
A.2.13 SIU
The VR4102 SIU is newly designed and is functionally compatible with NS16550 in contrast to that of the VR4101
which is originally designed by NEC. Their differences are as summarized below.
Item
VR4102
VR4102
Architecture
Functionally compatible with NS16550
NEC original
Maximum data rate
1.15 Mbps
115 kbps
IR communication
Available
Available
Data transfer
Read out of FIFO buffers by software
DMA
Character length
5, 6, 7, or 8 bits
7 or 8 bits
Stop bit length
1, 1.5 (for 5 bits), or 2 (for 6, 7, or 8 bits)
1 or 2
Parity check
Checked/generated is selectable
Checked/not generated
(substituted by software)
Framing error
Automatically detected
Automatically detected
Break transmission
Available
Available
Break detection
Automatically detected
Automatically detected
Receive overrun error
Automatically detected
Occurs receive data lost interrupt
Flow control pins
RTS#, CTS#, DTR#, DSR#, DCD#
RTS#, CTS#, DTR#, DSR#, DCD
Transmit data flow
16450 mode: from SIUTH register to transmit
shift register
FIFO mode: from FIFO (16 bytes) to
transmit shift register
From DMA (2K bytes) to SIUTXDATREG
Receive data flow
16450 mode: from receive shift register to
SIURB register
FIFO mode: from receive shift register to
FIFO (16 bytes)
From SIURXDATREG to DMA (2K bytes)



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