ADPD188GG datasheet(53/61 Pages) AD

53 / 61 page

Data Sheet

ADPD188GG

Rev. B | Page 53 of 61

Address

Data Bit

Default

Value

Access

Name

Description

0x1C

[15:14]

0x0

R/W

BG_COUNT_B

For Time Slot B, this is the number of times the ADC value

exceeds the BG_THRESH_B value during the float mode subtract

cycles before the BG_STATUS_B bit is set.

0: never set BG_STATUS_B.

1: set when BG_THRESH_B is exceeded 1 time.

2: set when BG_THRESH_B is exceeded 4 times.

3: set when BG_THRESH_B is exceeded 16 times.

[13:0]

0x0

R/W

BG_THRESH_B

The background threshold for Time Slot B that is compared

against the ADC result during the subtract cycles during float

mode. If the ADC result exceeds the value in this register,

BG_COUNT_B is incremented.

0x3E

[15:14]

0x0

R/W

FLT_LED_SELECT_A

Time Slot A LED selection for float LED mode.

0: no LED selected.

1: LED1.

2: LED2.

3: LED3.

R/W

Reserved

Write 0x0.

[12:8]

0x03

R/W

FLT_LED_WIDTH_A

Time Slot A LED pulse width for LED float mode in 1 µs steps.

[7:0]

0x20

R/W

FLT_LED_OFFSET_A

Time to first LED pulse in float mode for Time Slot A.

0x3F

[15:14]

0x0

R/W

FLT_LED_SELECT_B

Time Slot B LED selection for float LED mode.

0: no LED selected.

1: LED1.

2: LED2.

3: LED3.

R/W

Reserved

Write 0x0.

[12:8]

0x03

R/W

FLT_LED_WIDTH_B

Time Slot B LED pulse width for LED float mode in 1 µs steps.

[7:0]

0x20

R/W

FLT_LED_OFFSET_B

Time to first LED pulse in Float mode for Time Slot A.

0x58

[15:12]

0x0

R/W

Reserved

Reserved.

[11:10]

0x0

R/W

FLT_MATH34_B

Time Slot B control for adding and subtracting Sample 3 and

Sample 4 in a four-pulse sequence (or any multiple of four pulses,

for example, Sample 15 and Sample 16 in a 16-pulse sequence).

00: add third and fourth.

01: add third and subtract fourth.

10: subtract third and add fourth.

11: subtract third and fourth.

[9:8]

0x0

R/W

FLT_MATH34_A

Time Slot A control for adding and subtracting Sample 3 and

Sample 4 in a four-pulse sequence (or any multiple of four pulses,

for example, Sample 15 and Sample 16 in a 16-pulse sequence).

00: add third and fourth.

01: add third and subtract fourth.

10: subtract third and add fourth.

11: subtract third and fourth.

0x0

R/W

ENA_INT_AS_BUF

Set to 1 to enable the configuration of the integrator as a buffer in

TIA ADC mode.

[6:5]

0x0

R/W

FLT_MATH12_B

Time Slot B control for adding and subtracting Sample 1 and

Sample 2 in a four-pulse sequence (or any multiple of four pulses,

for example, Sample 13 and Sample 14 in a 16-pulse sequence).

00: add first and second.

01: add first and subtract second.

10: subtract first and add second.

11: subtract first and second.

[4:3]

0x0

R/W

Reserved

Write 0x0.

ADPD188GG Datasheet(PDF) 53 Page - Analog Devices

ADPD188GG Datasheet(HTML) 53 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

Datasheet Download

Link URL