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ADPD188GG

Data Sheet

Rev. B | Page 16 of 61

ADJUSTABLE SAMPLING FREQUENCY

ADPD188GG and Register 0x4B, Bits[5:0] further tunes this

clock for greater accuracy. The sampling frequency is governed

by an internal 32 kHz sample rate clock that also drives the

transition of the internal state machine. The maximum sampling

frequencies for some sample conditions are listed in Table 1. The

maximum sample frequency for all conditions, fSAMPLE,_MAX, is

determined by the following equation:

fSAMPLE_MAX = 1/(tA + t1 + tB + t2 + tSLEEP_MIN)

where tSLEEP_MIN is the minimum sleep time required between

samples. See the Dual Time Slot Operation section for the

definitions of tA, t1, tB, and t2.

If a given time slot is not in use, elements from that time slot do

not factor into the calculation. For example, if Time Slot A is

not in use, tA and t1 do not add to the sampling period and the

new maximum sampling frequency is calculated as follows:

fSAMPLE_MAX = 1/(tB + t2 + tSLEEP_MIN)

EXTERNAL SYNCHRONIZATION FOR SAMPLING

The ADPD188GG provides an option to use an external

synchronization signal to trigger the sampling periods. This

external sample synchronization signal can be provided either

on the GPIO0 pin or the GPIO1 pin. This functionality is

controlled by Register 0x4F, Bits[3:2]. When enabled, a rising

edge on the selected input specifies when the next sample cycle

occurs. When triggered, there is a delay of one to two internal

sampling clock (32 kHz) cycles, and then the normal start-up

sequence occurs. This sequence is the same as when the normal

sample timer provides the trigger. To enable the external

synchronization signal feature, use the following procedure:

1. Write 0x1 to Register 0x10 to enter program mode.

2. Write the appropriate value to Register 0x4F, Bits[3:2] to

select whether the GPIO0 pin or the GPIO1 pin specifies

when the next sample cycle occurs. Also, enable the

appropriate input buffer using Register 0x4F, Bit 1, for the

GPIO0 pin, or Register 0x4F, Bit 5, for the GPIO1 pin.

3. Write 0x4000 to Register 0x38.

4. Write 0x2 to Register 0x10 to start the sampling

operations.

5. Apply the external synchronization signal on the selected

pin at the desired rate; sampling occurs at that rate. As

with normal sampling operations, read the data using the

FIFO or the data registers. The maximum frequency

constraints also apply in this case.

Providing an External 32 kHz Clock

The ADPD188GG has an option for the user to provide an

external 32 kHz clock to the device for system synchronization

or for situations where a clock with better accuracy than the

internal 32 kHz clock is required. The external 32 kHz clock is

provided on the GPIO1 pin only. To enable the 32 kHz external

clock, use the following procedure at startup:

1. Drive the GPIO1 pin to a valid logic level or with the

desired 32 kHz clock prior to enabling the GPIO1 pin as

an input. Do not leave the pin floating prior to enabling it.

2. Write 0x1 to Register 0x4F, Bits[6:5] to enable the

GPIO1 pin as an input.

3. Write 0x2 to Register 0x4B, Bits[8:7] to configure the devices

to use an external 32 kHz clock. This setting disables the

internal 32 kHz clock and enables the external 32 kHz clock.

4. Write 0x1 to Register 0x10 to enter program mode.

5. Write additional control registers in any order while the

device is in program mode to configure the device as

required.

6. Write 0x2 to Register 0x10 to start the normal sampling

operation

STATE MACHINE OPERATION

During each time slot, the ADPD188GG operates according to

a state machine. The state machine operates in the sequence

shown in Figure 17.

STANDBY

ULTRALOW POWER MODE

NO DATA COLLECTION

ALL REGISTER VALUES ARE RETAINED.

PROGRAM

SAFE MODE FOR PROGRAMMING REGISTERS

NO DATA COLLECTION

DEVICE IS FULLY POWERED IN THIS MODE.

NORMAL OPERATION

LEDs ARE PULSED AND PHOTODIODES ARE SAMPLED

STANDARD DATA COLLECTION

DEVICE POWER IS CYCLED BY INTERNAL STATE MACHINE.

Figure 17. State Machine Operation Flowchart

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