ADPD188GG datasheet(25/61 Pages) AD

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Data Sheet

ADPD188GG

Rev. B | Page 25 of 61

To calibrate the 32 kHz clock,

Set the sampling frequency to the highest the system can

handle, such as 2000 Hz. Because the 32 kHz clock

controls sample timing, its frequency is readily accessible

via the GPIO0 pin. Configure the interrupt by writing the

appropriate value to Bits[2:0] in Register 0x02 and set the

interrupt to occur at the sampling frequency by writing

0x0 to Register 0x01, Bit 5 or Bit 6. Monitor the GPIO0 pin.

The interrupt frequency must match the set sample

frequency.

If the monitored interrupt frequency is less than the set

sampling frequency, decrease the CLK32K_ADJUST bits

(Register 0x4B, Bits[5:0]). If the monitored interrupt

frequency is larger than the set sampling frequency,

increase the CLK32K_ADJUST bits.

Repeat Step 1 until the monitored interrupt signal

frequency is close to the set sampling frequency.

Calibrating the 32 MHz Clock

This procedure calibrates items associated with the fine timing

within a sample period, such as LED pulse width and spacing,

and assumes that the 32 kHz clock is already calibrated.

To calibrate the 32 MHz clock,

Write 0x1 to Register 0x5F, Bit 0.

Enable the CLK_RATIO calculation by writing 0x1 to

counts the number of 32 MHz clock cycles in two cycles of

the 32 kHz clock. With this function enabled, this value is

stored in Register 0x0A, Bits[11:0] and nominally this ratio

is 2000 (0x07D0).

Calculate the 32 MHz clock error as follows:

Clock Error = 32 MHz × (1 − CLK_RATIO/2000)

Adjust the frequency by setting Bits[7:0] in Register 0x4D

per the following equation:

CLK32M_ADJUST = Clock Error/109 kHz

Write 0x0 to Register 0x50, Bit 5 to reset the CLK_RATIO

function.

Repeat Step 1 through Step 5 until the desired accuracy is

achieved.

Write 0x1 to Register 0x5F, Bit 0, and set the GPIO0 pin

back to the mode desired for normal operation.

OPTIONAL TIMING SIGNALS AVAILABLE ON

GPIO0 AND GPIO1

The ADPD188GG provides a number of different timing

signals, available via the GPIO0 and GPIO1 pins, to enable ease

of system synchronization and flexible triggering options. Each

GPIOx pin can be configured as an open-drain output if they

are sharing the bus with other drivers, or they can be

configured to always drive the bus. Both outputs also have

polarity control in situations where a timing signal must be

inverted from the default.

Table 16. GPIOx Control Settings

Pin Name

Setting Description

GPIO0

0x02, Bit 0

0: polarity active high

1: polarity active low

0x02, Bit 1

0: always drives the bus

1: drives the bus when asserted

0x02, Bit 2

0: disables the GPIO0 pin drive

1: enables the GPIO0 pin drive

GPIO1

0x02, Bit 8

0: polarity active high

1: polarity active low

0x02, Bit 9

0: always drives the bus

1: drives the bus when asserted

0x4F, Bit 6

0: disables the GPIO1 pin drive

1: enables the GPIO1 pin drive

The various available timing signals are controlled by the

settings in Register 0x0B, Bits[12:8] of this register control the

timing signals available on GPIO1, and Bits[4:0] control the

timing signals available on GPIO0. All of the timing signals

described in this data sheet are available on either (or both) of

the GPIO0 and GPIO1 pins. Timing diagrams are shown in

Figure 27 and Figure 28. The time slot settings used to generate

the timing diagrams are described in Table 17.

Table 17. ADPD188GG Settings Used for the Timing

Diagrams Shown in Figure 27 and Figure 28

Setting

Description

0x31

0x0118

Time Slot A: 1 LED pulse

0x36

0x0418

Time Slot B: 4 LED pulses

0x15

0x0120

Time Slot A decimation = 4, Time Slot B

decimation = 2

SLOT A

SLOT B

SLOT A

SLEEP

Figure 27. Optional Timing Signals Available on GPIOx—Register 0x0B, Bits[12:8] or Bits[4:0] = 0x02, 0x05, 0x06, 0x07, and 0x0F

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