ADPD188GG datasheet(18/61 Pages) AD

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ADPD188GG

Data Sheet

Rev. B | Page 18 of 61

LED Pulse and Sample

At each sampling period, the selected LED driver drives a series

of LED pulses, as shown in Figure 19. The magnitude, duration,

and number of pulses are programmable over the communications

interface. Each LED pulse coincides with a sensing period so

that the sensed value represents the total charge acquired on the

photodiode in response to only the corresponding LED pulse.

Charge, such as ambient light that does not correspond to the

LED pulse, is rejected.

After each LED pulse, the photodiode output relating to the

pulsed LED signal is sampled and converted to a digital value

by the 14-bit ADC. Each subsequent conversion within a

sampling period is summed with the previous result. Up to 255

pulse values from the ADC can be summed in an individual

sampling period. There is a 20-bit maximum range for each

sampling period.

Averaging

The ADPD188GG offers sample accumulation and averaging

functionality to increase signal resolution.

Within a sampling period, the AFE can sum up to 256 sequential

pulses. As shown in Figure 18, samples acquired by the AFE are

clipped to 20 bits at the output of the AFE. Additional resolution,

up to 27 bits, can be achieved by averaging between sampling

periods. This accumulated data of N samples is stored as 27-bit

values and can be read out directly by using the 32-bit output

registers or the 32-bit FIFO configuration.

When using the averaging feature set up by the register, subse-

quent pulses can be averaged by powers of 2. The user can

select from 2, 4, 8, …, up to 128 samples to be averaged. Pulse

data is still acquired by the AFE at the sampling frequency,

fSAMPLE (see Register 0x12), but new data is written to the

registers at the rate of fSAMPLE/N every Nth sample. This new data

consists of the sum of the previous N samples. The full 32-bit

sum is stored in the 32-bit registers. However, before sending

this data to the FIFO, a divide by N operation occurs. This

divide operation maintains bit depth to prevent clipping on the

FIFO.

Use this between sample averaging to lower the noise while

maintaining 16-bit resolution. If the pulse count registers are

kept to 8 or less, the 16-bit width is never exceeded. Therefore,

when using Register 0x15 to average subsequent pulses, many

pulses can be accumulated without exceeding the 16-bit word

width. This setting can reduce the number of FIFO reads

required by the host processor.

Data Read

The host processor reads output data from the ADPD188GG

via the communications interface, from the data registers, or from

the FIFO. New output data is made available every N samples,

where N is the user configured averaging factor. The averaging

factors for Time Slot A and Time Slot B are configurable

independently of each other. If the factors are the same, both

time slots can be configured to save data to the FIFO. If the two

averaging factors are different, only one time slot can save data

to the FIFO; data from the other time slot can be read from the

output registers.

The data read operations are described in more detail in the

Reading Data section.

0.5

1.0

1.5

2.0

2.5

3.0

TIME (Seconds)

OPTICAL SAMPLING

LOCATIONS

NUMBER OF LED PULSES (

nA OR nB)

LED

CURRENT

(ILED)

SHOWN WITH fSAMPLE = 10Hz

Figure 19. Example of a PPG Signal Sampled at a Data Rate of 10 Hz Using Five Pulses per Sample

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