ADPD188GG datasheet(55/61 Pages) AD

55 / 61 page

Data Sheet

ADPD188GG

Rev. B | Page 55 of 61

SYSTEM REGISTERS

Table 32. System Registers

Address

Data Bit

Default

Value

Access

Name

Description

0x00

[15:8]

0x00

R/W

FIFO_SAMPLES

FIFO status. Number of available bytes to be read from the FIFO.

When comparing this to the FIFO length threshold (Register 0x06,

Bits[13:8]), note that the FIFO status value is in bytes and the FIFO

length threshold is in words, where one word = two bytes.

Write 1 to Bit 15 to clear the contents of the FIFO.

0x0

R/W

Reserved

Write 0x1 to clear this bit to 0x0.

0x0

R/W

SLOTB_INT

Time Slot B interrupt. Describes the type of interrupt event. A 1

indicates an interrupt of a particular event type has occurred. Write

a 1 to clear the corresponding interrupt. After clearing, the register

goes to 0. Writing a 0 to this register has no effect.

0x0

R/W

SLOTA_INT

Time Slot A interrupt. Describes the type of interrupt event. A 1

indicates an interrupt of a particular event type has occurred. Write a

1 to clear the corresponding interrupt. After clearing, the register

goes to 0. Writing a 0 to this register has no effect.

[4:0]

0x00

R/W

Reserved

Write 0x1F to clear these bits to 0x00.

0x01

[15:9]

0x00

R/W

Reserved

Write 0x00.

0x1

R/W

FIFO_INT_MASK

Sends an interrupt when the FIFO data length has exceeded the

FIFO length threshold in Register 0x06, Bits[13:8]. A 0 enables the

interrupt.

0x1

R/W

Reserved

Write 0x1.

0x1

R/W

SLOTB_INT_MASK

Sends an interrupt on the Time Slot B sample. Write a 1 to disable

the interrupt. Write a 0 to enable the interrupt.

0x1

R/W

SLOTA_INT_MASK

Sends an interrupt on the Time Slot A sample. Write a 1 to disable

the interrupt. Write a 0 to enable the interrupt.

[4:0]

0x1F

R/W

Reserved

Write 0x1F.

0x02

[15:10]

0x00

R/W

Reserved

Write 0x0000.

0x0

R/W

GPIO1_DRV

GPIO1 drive.

0: the GPIO1 pin is always driven.

1: the GPIO1 pin is driven when the interrupt is asserted; otherwise,

it is left floating and requires a pull-up or pull-down resistor,

depending on polarity (operates as open drain). Use this setting if

multiple devices must share the GPIO1 pin.

0x0

R/W

GPIO1_POL

GPIO1 polarity.

0: the GPIO1 pin is active high.

1: the GPIO1 pin is active low.

[7:3]

0x00

R/W

Reserved

Write 0x00.

0x0

R/W

GPIO0_ENA

GPIO0 pin enable.

0: disable the GPIO0 pin. The GPIO0 pin floats, regardless of

interrupt status. The status register (Address 0x00) remains active.

1: enable the GPIO0 pin.

0x0

R/W

GPIO0_DRV

GPIO0 drive.

0: the GPIO0 pin is always driven.

1: the GPIO0 pin is driven when the interrupt is asserted; otherwise,

it is left floating and requires a pull-up or pull-down resistor,

depending on polarity (operates as open drain). Use this setting if

multiple devices must share the GPIO0 pin.

0x0

R/W

GPIO0_POL

GPIO0 polarity.

0: the GPIO0 pin is active high.

1: the GPIO0 pin is active low.

ADPD188GG Datasheet(PDF) 55 Page - Analog Devices

ADPD188GG Datasheet(HTML) 55 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

Datasheet Download

Link URL