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ADPD188GG Datasheet(PDF) 56 Page - Analog Devices

Part # ADPD188GG
Description  Integrated Optical Module with Ambient Light Rejection and Two LEDs
PDF  61 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADPD188GG Datasheet(HTML) 56 Page - Analog Devices

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ADPD188GG
Data Sheet
Rev. B | Page 56 of 61
Address
Data Bit
Default
Value
Access
Name
Description
0x06
[15:14]
0x0
R/W
Reserved
Write 0x0.
[13:8]
0x00
R/W
FIFO_THRESH
FIFO length threshold. An interrupt is generated when the number of
data-words in the FIFO exceeds the value in FIFO_THRESH. The interrupt
pin automatically deasserts when the number of data-words available
in the FIFO no longer exceeds the value in FIFO_THRESH.
[7:0]
0x00
R/W
Reserved
Write 0x00.
0x08
[15:8]
0x0A
R
REV_NUM
Revision number.
[7:0]
0x16
R
DEV_ID
Device ID.
0x09
[15:8]
0x00
W
ADDRESS_WRITE_KEY
Write 0xAD when writing to SLAVE_ADDRESS. Otherwise, do not access.
[7:1]
0x64
R/W
SLAVE_ADDRESS
I2C slave address.
0
0x0
R
Reserved
Do not access.
0x0A
[15:12]
0x0
R
Reserved
Write 0x0.
[11:0]
0x000
R
CLK_RATIO
When the CLK32M_CAL_EN bit (Register 0x50, Bit 5) is set, the
device calculates the number of 32 MHz clock cycles in two cycles of
the 32 kHz clock. The result, nominally 2000 (0x07D0), is stored in
the CLK_RATIO bits.
0x0B
[15:13]
0x0
R/W
Reserved
Write 0x0.
[12:8]
0x00
R/W
GPIO1_ALT_CFG
Alternate configuration for the GPIO1 pin.
0x00: GPIO1 is backward compatible to the ADPD103 PDSO pin
functionality.
0x01: interrupt function provided on GPIO1, as defined in Register 0x01.
0x02: asserts at the start of the first time slot, deasserts at end of last
time slot.
0x05: Time Slot A pulse output.
0x06: Time Slot B pulse output.
0x07: pulse output of both time slots.
0x0C: output data cycle occurred for Time Slot A.
0x0D: output data cycle occurred for Time Slot B.
0x0E: output data cycle occurred.
0x0F: toggles on every sample, which provides a signal at half the
sampling rate.
0x10: output = 0.
0x11: output = 1.
0x13: 32 kHz oscillator output.
Remaining settings are not supported.
[7:5]
0x0
R/W
Reserved
Write 0x0.
[4:0]
0x00
R/W
GPIO0_ALT_CFG
Alternate configuration for the GPIO0 pin.
0x0: GPIO0 is backward compatible to the ADPD103 INT pin
functionality.
0x1: interrupt function provided on GPIO0, as defined in Register 0x01.
0x2: asserts at the start of the first time slot, deasserts at end of last
time slot.
0x5: Time Slot A pulse output.
0x6: Time Slot B pulse output.
0x7: pulse output of both time slots.
0xC: output data cycle occurred for Time Slot A.
0xD: output data cycle occurred for Time Slot B.
0xE: output data cycle occurred.
0xF: toggles on every sample, which provides a signal at half the
sampling rate.
0x10: output = 0.
0x11: output = 1.
0x13: 32 kHz oscillator output.
Remaining settings are not supported.



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