ADPD188GG datasheet(19/61 Pages) AD

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Data Sheet

ADPD188GG

Rev. B | Page 19 of 61

COMMUNICATIONS INTERFACE

The ADPD188GG supports both an SPI and I2C serial interface,

although only one can be used at any given time in the actual

application. All internal registers are accessed through the

selected communications interface.

I2C INTERFACE

The ADPD188GG I2C conforms to the UM10204 I2C-Bus

Specification and User Manual, Rev. 05—9 October 2012,

available from NXP Semiconductors. The device supports fast

mode (400 kbps) data transfer. Register read and write operations

are supported, as shown in Figure 20. The 7-bit I2C slave address

for the device is 0x64. If the I2C interface is being used, the CS

pin must be pulled high to disable the SPI port.

Single-word and multiword read operations are supported. For

a single register read, the host sends a no acknowledge (NACK)

after the second data byte is read and a new register address is

needed for each access.

For multiword operations, each pair of data bytes is followed by

an acknowledge (ACK) from the host until the last byte of the

last word is read. The host indicates the last read word by

sending a no acknowledge. When reading from the FIFO

(Register 0x60), the data is automatically advanced to the next

word in the FIFO, and the space is freed. When reading from

other registers, the register address is automatically advanced to

the next register, allowing the user to read without readdressing

each register, thereby reducing the amount of overhead

required to read multiple registers. This auto-increment does

not apply to the register that precedes the FIFO, Register 0x5F,

or the last data register, Register 0x7E.

All register writes are single-word only and require 16 bits

(one word) of data.

The software reset (Register 0x0F, Bit 0) returns an

acknowledge. The device then returns to standby mode with all

registers in the default state.

Table 13. Definitions of I2C Terminology

Term

Description

SCL

Serial clock.

SDA

Serial address and data.

Master

The device that initiates a transfer, generates clock signals, and terminates a transfer.

Slave

The device addressed by a master. The ADPD188GG operates as a slave device.

Start (S)

A high to low transition on the SDA line while SCL is high; all transactions begin with a start condition.

Start (Sr)

Repeated start condition.

Stop (P)

A low to high transition on the SDA line while SCL is high. A stop condition terminates all transactions.

ACK

During the acknowledge (ACK) or no acknowledge (NACK) clock pulse, the SDA line is pulled low, and it remains low.

NACK

During the ACK or NACK clock pulse, the SDA line remains high.

Slave Address

After a start (S), a 7-bit slave address is sent, which is followed by a data direction bit (read or write).

Read (R)

A 1 indicates a request for data.

Write (W)

A 0 indicates a transmission.

NOTES

1. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING.

MASTER START

SLAVE ADDRESS + WRITE

SLAVE

ACK

MASTER START

SLAVE ADDRESS + WRITE

ACK/NACK

STOP

SLAVE

ACK

DATA[7:0]

DATA[15:8]

SLAVE ADDRESS + READ

ACK

DATA[7:0]

DATA[15:8]

STOP

ACK

DATA TRANSFERRED

MASTER START

SLAVE ADDRESS + WRITE

NACK

STOP

SLAVE

ACK

DATA[7:0]

SLAVE ADDRESS + READ

ACK

DATA[15:8]

ACK

I2C WRITE

I2C SINGLE-WORD READ MODE

I2C MULTIWORD READ MODE

Figure 20. I2C Write and Read Operations

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