ADPD1081 datasheet(29/74 Pages) AD

29 / 74 page

Data Sheet

ADPD1080/ADPD1081

Rev. C | Page 29 of 74

NOTES

1. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING.

MASTER START

SLAVE ADDRESS + WRITE

SLAVE

ACK

MASTER START

SLAVE ADDRESS + WRITE

ACK/NACK

STOP

SLAVE

ACK

DATA[7:0]

DATA[15:8]

SLAVE ADDRESS + READ

ACK

DATA[7:0]

DATA[15:8]

STOP

ACK

DATA TRANSFERRED

MASTER START

SLAVE ADDRESS + WRITE

NACK

STOP

SLAVE

ACK

DATA[7:0]

SLAVE ADDRESS + READ

ACK

DATA[15:8]

ACK

I2C WRITE

I2C SINGLE WORD READ MODE

I2C MULTIWORD READ MODE

Figure 32. I2C Write and Read Operations

SPI PORT

The ADPD1081 is a SPI only device. It does not support the I2C

interface. The SPI port uses a 4-wire interface, consisting of the

CS, MOSI, MISO, and SCLK signals, and it is always a slave port.

The CS signal goes low at the beginning of a transaction and high

at the end of a transaction. The SCLK signal latches MOSI on a

low to high transition. The MISO data is shifted out of the device

on the falling edge of SCLK and must be clocked into a receiving

device, such as a microcontroller, on the SCLK rising edge. The

MOSI signal carries the serial input data, and the MISO signal

carries the serial output data. The MISO signal remains three

state until a read operation is requested, which allows other

SPI-compatible peripherals to share the same MISO line. All SPI

transactions have the same basic format shown in Table 20. A

timing diagram is shown in Figure 4. Write all data MSB first.

Table 20. Generic Control Word Sequence

Byte 0

Byte 1

Byte 2

Subsequent Bytes

Address[6:0],

W/R

Data[15:8]

Data[7:0]

Data[15:8], Data[7:0]

The first byte written in a SPI transaction is a 7-bit address,

which is the location of the address being accessed, followed by

the W/R bit. This bit determines whether the communication is

a write (Logic Level 1) or a read (Logic Level 0). This format is

shown in Table 21.

Table 21. SPI Address and Write/R Byte Format

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

W/R

Data on the MOSI pin is captured on the rising edge of the

clock, and data is propagated on the MISO pin on the falling

edge of the clock. The maximum read and write speed for the

SPI slave port is 10 MHz. See Figure 4 for the SPI timing

diagram, and see Table 7 for the SPI timing specifications.

A sample timing diagram for a multiple word SPI write operation

to a register is shown in Figure 33. A sample timing diagram of

a single-word SPI read operation is shown in Figure 34. The

MISO pin transitions from being three-state to being driven

following the reception of a valid R bit. In this example, Byte 0

contains the address and the W/R bit and subsequent bytes

carry the data. A sample timing diagram of a multiple word SPI

read operation is shown in Figure 35. In Figure 33 to Figure 35,

rising edges on SCLK are indicated with an arrow, signifying

that the data lines are sampled on the rising edge.

When performing multiple word reads or writes, the data

address is automatically incremented to the next consecutive

address for subsequent transactions except for Address 0x5F

(DATA_ACCESS_CTL), Address 0x60 (FIFO_ACCESS), and

Address 0x7F (B_PD4_HIGH).

ADPD1081 Datasheet(PDF) 29 Page - Analog Devices

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