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ADPD1081 Datasheet(PDF) 7 Page - Analog Devices

Part # ADPD1081
Description  Photometric Front Ends
PDF  74 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADPD1081 Datasheet(HTML) 7 Page - Analog Devices

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Data Sheet
ADPD1080/ADPD1081
Rev. C | Page 7 of 74
PERFORMANCE SPECIFICATIONS
AVDD = DVDD = 1.8 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DATA ACQUISITION
Resolution
Single pulse
14
Bits
Sample
64 to 255 pulses
20
Bits
Data Read
64 to 255 pulses and sample average = 128
27
Bits
LED DRIVER
LED Current Slew Rate1
TA = 25°C; ILED = 70 mA
Rising
Slew rate control setting = 0
240
mA/µs
Slew rate control setting = 7
1400
mA/µs
Falling
Slew rate control setting = 0, 1, or 2
3200
mA/µs
Slew rate control setting = 6 or 7
4500
mA/µs
LED Peak Current
LED pulse enabled
370
mA
Driver Compliance Voltage
Voltage above ground required for LED driver operation
0.6
V
LED PERIOD
AFE width = 4 µs2
19
µs
AFE width = 3 µs
17
µs
Sampling Frequency3
Time Slot A or Time Slot B; normal mode; 1 pulse;
SLOTA_LED_OFFSET = 23 µs; SLOTA_PERIOD = 19 µs
0.122
2000
Hz
Both time slots; normal mode; 1 pulse;
SLOTA_LED_OFFSET = 23 µs; SLOTA_PERIOD = 19 µs
0.122
1600
Hz
Time Slot A or Time Slot B; normal mode; 8 pulses;
SLOTA_LED_OFFSET = 23 µs; SLOTA_PERIOD = 19 µs
0.122
1600
Hz
Both time slots; normal mode; 8 pulses;
SLOTA_LED_OFFSET = 23 µs; SLOTA_PERIOD = 19 µs
0.122
1000
Hz
CATHODE PIN (PDC) VOLTAGE
During All Sampling Periods
Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 14
1.8
V
Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 0
1.3
V
During Time Slot A Sampling
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x04
1.8
V
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x1
1.3
V
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x2
1.55
V
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x35
0
V
During Time Slot B Sampling
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x04
1.8
V
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x1
1.3
V
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x2
1.55
V
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x35
0
V
During Sleep Periods
Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 1
1.8
V
Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 0
1.3
V
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x0
1.8
V
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x1
1.3
V
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x2
1.55
V
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x3
0
V
PHOTODIODE INPUT PINS/ANODE VOLTAGE
During All Sampling Periods
1.3
V
During Sleep Periods
Cathode voltage
V
1
LED inductance is negligible for these values. The effective slew rate slows with increased inductance.
2
Minimum LED period = (2 × AFE width) + 5 µs.
3
The maximum values in this specification are the internal ADC sampling rates in normal mode using the internal 32 kHz state machine clock. The I2C read rates in some
configurations may limit the output data rate.
4
This mode can induce additional noise and is not recommended unless necessary. The 1.8 V setting uses VDD, which contains greater amounts of differential voltage
noise with respect to the anode voltage.
5
This setting is not recommended for photodiodes because it causes a 1.3 V forward-bias of the photodiode.



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