ADPD1081 datasheet(69/74 Pages) AD

69 / 74 page

Data Sheet

ADPD1080/ADPD1081

Rev. C | Page 69 of 74

Address

Data Bit

Default

Value

Access

Name

Description

[11:9]

0x0

R/W

Reserved

Reserved.

[8:6]

0x0

R/W

SLOTB_FIFO_MODE

Time Slot B FIFO data format.

0: no data to FIFO.

1: 16-bit sum of all four channels.

2: 32-bit sum of all four channels.

4: four channels of 16-bit sample data for Time Slot B.

6: four channels of 32-bit extended sample data for Time Slot B.

Others: reserved.

The selected Time Slot B data is saved in the FIFO. Available only if

Time Slot A has the same averaging factor, N (Register 0x15, Bits[10:8]

= Bits[6:4]), or if Time Slot A is not saving data to the FIFO (Register 0x11,

Bits[4:2] = 0).

0x0

R/W

SLOTB_EN

Time Slot B enable. 1: enables Time Slot B.

[4:2]

0x0

R/W

SLOTA_FIFO_MODE

Time Slot A FIFO data format.

0: no data to FIFO.

1: 16-bit sum of all four channels.

2: 32-bit sum of all four channels.

4: four channels of 16-bit sample data for Time Slot A.

6: four channels of 32-bit extended sample data for Time Slot A.

Others: reserved.

0x0

R/W

Reserved

Write 0x0.

0x0

R/W

SLOTA_EN

Time Slot A enable. 1: enables Time Slot A.

0x38

[15:0]

0x0000

R/W

EXT_SYNC_STARTUP

Write 0x4000 when EXT_SYNC_SEL is 01 or 10. Otherwise, write 0x0.

0x4B

[15:9]

0x13

R/W

Reserved

Write 0x13.

0x0

R/W

CLK32K_BYP

Bypass internal 32 kHz oscillator.

0x0: normal operation.

0x1: provide external clock on the GPIO1 pin. The user must set

0x0

R/W

CLK32K_EN

Sample clock power-up. Enables the data sample clock.

0x0: clock disabled.

0x1: normal operation.

0x0

R/W

Reserved

Write 0x0.

[5:0]

0x12

R/W

CLK32K_ADJUST

Data sampling (32 kHz) clock frequency adjust. This register is used

to calibrate the sample frequency of the device to achieve high

precision on the data rate as defined in Register 0x12. Adjusts the

sample master 32 kHz clock by 0.6 kHz per LSB. For a 100 Hz sample

rate as defined in Register 0x12, 1 LSB of Register 0x4B, Bits[5:0], is

1.9 Hz.

Note that a larger value produces a lower frequency. See the Clocks

and Timing Calibration section for more information regarding clock

adjustment.

00 0000: maximum frequency.

10 0010: typical center frequency.

11 1111: minimum frequency.

0x4D

[15:8]

0x00

R/W

Reserved

Write 0x00.

[7:0]

0x98

R/W

CLK32M_ADJUST

Internal timing (32 MHz) clock frequency adjust. This register is used

to calibrate the internal clock of the device to achieve precisely

timed LED pulses. Adjusts the 32 MHz clock by 109 kHz per LSB.

See the Clocks and Timing Calibration section for more information

regarding clock adjustment.

0000 0000: minimum frequency.

1001 1000: default frequency.

1111 1111: maximum frequency.

ADPD1081 Datasheet(PDF) 69 Page - Analog Devices

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