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ADPD1081 Datasheet(PDF) 61 Page - Analog Devices |
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ADPD1081 Datasheet(HTML) 61 Page - Analog Devices |
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61 / 74 page ![]() Data Sheet ADPD1080/ADPD1081 Rev. C | Page 61 of 74 Address Data Bit Default Value Access Name Description 0x54 [15:14] 0x0 R/W Reserved Write 0x0. [13:12] 0x0 R/W SLEEP_V_CATHODE If Bit 7 = 1; this setting is applied to the cathode voltage while the device is in sleep mode. 0x0: VDD. 0x1: AFE VREF during idle, VDD during sleep. 0x2: floating. 0x3: 0.0 V. [11:10] 0x0 R/W SLOTB_V_CATHODE If Bit 7 = 1; this setting is applied to the cathode voltage while the device is in Time Slot B operation. The anode voltage is determined by Register 0x44, Bits[5:4]. 0x0: VDD (1.8 V). 0x1: equal to PD anode voltage. 0x2: sets a reverse PD bias of ~250 mV (recommended setting). 0x3: 0.0 V (this forward biases a diode at the input). [9:8] 0x0 R/W SLOTA_V_CATHODE If Bit 7 = 1; this setting is applied to the cathode voltage while the device is in Time Slot A operation. The anode voltage is determined by Register 0x42, Bits[5:4]. 0x0: VDD (1.8 V). 0x1: equal to PD anode voltage. 0x2: sets a reverse PD bias of ~250 mV (recommended setting). 0x3: 0.0 V (this forward biases a diode at the input). 7 0x0 R/W REG54_VCAT_ENABLE 0: use the cathode voltage settings defined by Register 0x3C, Bit 9. 1: override Register 0x3C, Bit 9 with cathode settings defined by Register 0x54, Bits[13:8]. [6:0] 0x20 R/W Reserved Reserved. 0x55 [15:12] 0x0 R/W Reserved Write 0x0. [11:10] 0x0 R/W SLOTB_TIA_GAIN_4 TIA gain for Time Slot B, Channel 4 when Register 0x44, Bit 6 = 1. 0: 200 kΩ. 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. [9:8] 0x0 R/W SLOTB_TIA_GAIN_3 TIA gain for Time Slot B, Channel 3 when Register 0x44, Bit 6 = 1. 0: 200 kΩ 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. [7:6] 0x0 R/W SLOTB_TIA_GAIN_2 TIA gain for Time Slot B, Channel 2 when Register 0x44, Bit 6 = 1. 0: 200 kΩ 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. [5:4] 0x0 R/W SLOTA_TIA_GAIN_4 TIA gain for Time Slot A, Channel 4 when Register 0x42, Bit 6 = 1. 0: 200 kΩ 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. |
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