ADPD1081 datasheet(47/74 Pages) AD

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Data Sheet

ADPD1080/ADPD1081

Rev. C | Page 47 of 74

FLOAT MODE

The ADPD1080/ADPD1081 has a unique operating mode,

float mode, that allows excellent SNR at low power in low

light situations. In float mode, the photodiode is first

preconditioned to a known state and then the photodiode

anode is disconnected from the receive path of the ADPD1080/

ADPD1081 for a preset amount of float time. During the float

time, light falls on the photodiode, either from ambient light,

pulsed LED light, or a combination of the two depending on

the operating mode. Charge from the sensor is stored directly

on the capacitance of the sensor. At the end of the float time,

the photodiode switches back into the receive path of the

ADPD1080/ADPD1081 and an inrush of the accumulated

charge occurs, which is subsequently integrated by the integrator

of the ADPD1080/ADPD1081, allowing the maximum amount

of charge to be processed per pulse with the minimum amount

of noise added by the signal path. The charge is integrated

externally on the capacitance of the photodiode for as long as

it takes to acquire maximum charge, independent of the

amplifiers of the signal path, which adds noise to the signal.

Amplifier and ADC noise values are constant for a given

measurement. For optimal SNR, it is desirable to have a greater

amount of signal (charge) per measurement. In normal mode,

because the pulse time is fixed, the charge per measurement can

be increased only by increasing the LED drive current. For high

light conditions, this is sufficient. In low light conditions,

however, there is a limit to the available current. In addition,

high current pulses can cause ground noise in some systems.

Green LEDs have lower efficiency at high currents, and many

battery designs do not deliver high current pulses as efficiently.

Float mode allows the user the flexibility to increase the

amount of charge per measurement by either increasing the

LED drive current or by increasing the float time. This

flexibility is especially useful in low current transfer ratio (CTR)

conditions, for example, 10 nA/mA, where normal mode

requires multiple pulses to achieve an acceptable level of SNR.

In float mode, the signal path bypasses the BPF and uses only

the TIA and integrator. In normal mode, the shape of the pulse

is known (typically either 2 µs or 3 µs) and is consistent across

devices and conditions. The shape of the signal coming through

the BPF is also predictable, which allows a user to align the

integrator timing with the zero-crossing of the filtered signal.

In float mode, the shape of the signal produced by the charge

dump can differ across devices and conditions. A filtered signal

cannot be reliably aligned; therefore, the BPF cannot be used.

In float mode, the entire charge dump is integrated in the

negative cycle of the integrator and the positive cycle cancels

any offsets.

Float Mode Measurement Cycle

Figure 52 shows the float mode measurement cycle timing

diagram, and the following details the points shown:

•

The precondition period is shown prior to Point A. The

photodiode is connected to the TIA, and the photocurrent

flows into the TIA. The photodiode anode is held at 0.9 V

(Register 0x42 and Register 0x44, Bits[5:4] = 0x2 sets

TIA_VREF = 0.9 V). The photodiode is reverse biased

to a maximum reverse bias of ~250 mV by setting

0x2 (for Time Slot A). At this point, the output of the TIA

(TIA_OUT) = TIA_VREF − (IPD × RF), where IPD is the

current flowing from the PD into the ADPD1080/

ADPD1081 input, and the integrator is off.

•

At Point A, the photodiode is disconnected from the

receive path. Light continues to fall on the photodiode,

producing a charge that accumulates directly on the

photodiode capacitance. As the charge accumulates, the

voltage at the floating photodiode anode rises. The TIA is

disconnected from the input to the ADPD1080/ADPD1081

so that no current flows through the TIA, and the TIA

output is at TIA_VREF. Just prior to Point B, the integrator

resets to 0. In the Float Mode for Synchronous LED

Measurements section, the LED pulses during the time

period between Point A and Point D. Float times of <4 µs

are not allowed.

•

At Point B, the integrator begins its positive integration

phase. Small dc offsets between the TIA output and the

integrator reference causes the integrator output to ramp

up for positive offsets or ramp down for negative offsets.

The photodiode continues to accumulate charge during

this period.

•

At Point C, the integrator begins its negative integration

phase. This reversal in polarity begins to cancel any signal

caused by offsets. This offset cancellation continues through

Point F, where all offsets are cancelled completely.

•

At Point D, the photodiode switches into the receive path

where all the charge that has accumulated on the photo-

diode capacitance during the float time is dumped into the

TIA. The typical charge dump time is less than 2 µs. As

the current flows through the TIA, the output of the TIA

responds with a large negative signal. Because the integrator

is in the negative integration phase at this point, the output

of the integrator rises as the input current to the device

integrates back to total charge. Between Point D and Point

E, any light incident on the photodiode produces

additional photocurrent, which is immediately integrated

by the integrator as charge.

•

At Point E, the TIA disconnects from the receive path and

the TIA output returns to TIA_VREF. Between Point E

and Point F, the integrator completes the negative

integration phase and cancellation of the offsets.

•

At Point F, the integrator output is held until sampled by

the ADC.

ADPD1081 Datasheet(PDF) 47 Page - Analog Devices

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