ADPD1081 datasheet(40/74 Pages) AD

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ADPD1080/ADPD1081

Data Sheet

Rev. C | Page 40 of 74

Improving SNR Using Integrator Chopping

The last stage in the analog front end that is integrated into the

ADPD1080/ADPD1081 data path is a charge integrator. The

integrator uses an on and off integration sequence, synchronized

to the emitted light pulse, which acts as an additional high-pass

filter to remove offsets, drifts, and low frequency noise from the

previous stages. However, the integrating amplifier can itself

introduce low frequency signal content at a low level. The

ADPD1080/ADPD1081 have an integrator chop mode that

enables additional chopping in the digital domain to remove

this signal. This chopping is achieved by using even numbers of

pulses per sample and inverting the integration sequence for

half of those sequences. In the calculation to combine the

digitized result of each of the pulses of the sample, the sequences

with an inverted integrator sequence are subtracted and the

sequences with a normal integrator sequence are added. An

example diagram of the integrator chopping sequence is shown

in Figure 46.

The result is that any low frequency signal contribution from

the integrator is eliminated, leaving only the integrated signal,

which results in higher SNR, especially at higher numbers of

pulses and at lower TIA gains where the noise contribution of

the integrator becomes more pronounced.

Digital chopping is enabled using the registers and bits detailed

in Table 25. The bit fields define the chopping operation for the

first four pulses. This 4-bit sequence is then repeated for all

subsequent pulses. In Figure 46, a sequence is shown where the

second and fourth pulses are inverted, whereas the first and third

pulses remain in the default polarity (noninverted). This configura-

tion is achieved by setting Register 0x17, Bits[3:0] = 0xA and

respectively. To complete the operation, the math must be

adjusted using Register 0x58. In this example, set Register 0x58,

Bits[9:8] and Register 0x58, Bits[11:10] to b01 to add the third

pulse and subtract the fourth pulse for Time Slot A and Time

Slot B, respectively. Set Register 0x58, Bits[2:1] and Register

0x58, Bits[6:5] to b01 to add the first pulse and subtract the

second pulse for Time Slot A and Time Slot B, respectively. This

sequence then repeats for every subsequent sequence of four

pulses. An even number of pulses must be used with integrator

chop mode.

When using integrator chop mode, the ADC offset registers

(Register 0x18 through Register 0x1B for Time Slot A, and

set to 0. These settings are required because any digital offsets

at the output of the ADC are automatically eliminated when the

math is adjusted to subtract the inverted integration sequences

while the default integration sequences are added. Integrator

chop mode also eliminates the need to manually null the ADC

offsets at startup in a typical application. Note that the elimination

of the offset using chop mode may clip at least half of the noise

signal when no input signal is present, which makes measuring

the noise floor during characterization of the system difficult.

For this reason, perform noise floor characterization of the system

either with chop mode disabled or with chop mode enabled but

with a minimal signal present at the input that increases the

noise floor enough such that it is no longer clipped.

LED

PULSE 1

+–

–

+–

–

PULSE 2

PULSE 3

PULSE 4

BAND-PASS

FILTER

OUTPUT

ADC

INTEGRATOR

SEQUENCE

Figure 46. Diagram of Integrator Chopping Sequence

Table 25. Register Settings for Integrator Chop Mode

Hex

Addr.

Data

Bit(s)

Bit Name

Description

0x17

[3:0]

INTEG_ORDER_A

Integration sequence order for Time Slot A. Each bit corresponds to the polarity of the integration

sequence of a single pulse in a four-pulse sequence. Bit 0 controls the integration sequence of

Pulse 1, Bit 1 controls Pulse 2, Bit 2 controls Pulse 3, and Bit 3 controls Pulse 4. After four pulses, the

sequence repeats.

0: normal integration sequence.

1: reversed integration sequence.

0x1D

[3:0]

INTEG_ORDER_B

Integration sequence order for Time Slot B. Each bit corresponds to the polarity of the integration

sequence of a single pulse in a four-pulse sequence. Bit 0 controls the integration sequence of

Pulse 1, Bit 1 controls Pulse 2, Bit 2 controls Pulse 3, and Bit 3 controls Pulse 4. After four pulses, the

sequence repeats.

0: normal integration sequence.

1: reversed integration sequence

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