ADPD1081 datasheet(70/74 Pages) AD

70 / 74 page

ADPD1080/ADPD1081

Data Sheet

Rev. C | Page 70 of 74

Address

Data Bit

Default

Value

Access

Name

Description

0x4F

[15:8]

0x20

R/W

Reserved

Write 0x20.

0x1

R/W

Reserved

Write 0x1.

0x0

R/W

GPIO1_OE

GPIO1 pin output enable.

0x0

R/W

GPIO1_IE

GPIO1 pin input enable.

0x1

R/W

Reserved

Write 0x1.

[3:2]

0x0

R/W

EXT_SYNC_SEL

Sample sync select.

00: use the internal 32 kHz clock with FSAMPLE to select sample

timings.

01: use the GPIO0 pin to trigger sample cycle.

10: use the GPIO1 pin to trigger sample cycle.

11: reserved.

0x0

R/W

GPIO0_IE

GPIO0 pin input enable.

0x0

R/W

Reserved

Write 0x0.

0x50

[15:7]

0x000

R/W

Reserved

Write 0x000.

0x0

R/W

GPIO1_CTRL

Controls the GPIO1 output when the GPIO1 output is enabled

(GPIO1_OE = 0x1).

0x0: GPIO1 output driven low.

0x1: GPIO1 output driven by the AFE power-down signal.

0x0

R/W

CLK32M_CAL_EN

As part of the 32 MHz clock calibration routine, write 1 to begin the

clock ratio calculation. Read the result of this calculation from the

CLK_RATIO bits in Register 0x0A.

Reset this bit to 0 prior to reinitiating the calculation.

[4:0]

0x00

R/W

Reserved

Write 0x0.

0x5F

[15:3]

0x0000

R/W

Reserved

Write 0x0000.

0x0

R/W

SLOTB_DATA_HOLD

Setting this bit prevents the update of the data registers corresponding

to Time Slot B. Set this bit to ensure that unread data registers are not

updated, guaranteeing a contiguous set of data from all four

photodiode channels.

1: hold data registers for Time Slot B.

0: allow data register update.

0x0

R/W

SLOTA_DATA_HOLD

Setting this bit prevents the update of the data registers corresponding

to Time Slot A. Set this bit to ensure that unread data registers are not

updated, guaranteeing a contiguous set of data from all four

photodiode channels.

1: hold data registers for Time Slot A.

0: allow data register update.

0x0

R/W

DIGITAL_CLOCK_ENA

Set to 1 in order to enable the 32 MHz clock when calibrating the

32 MHz clock. Always disable the 32 MHz clock following the

calibration by resetting this bit to 0.

ADPD1081 Datasheet(PDF) 70 Page - Analog Devices

ADPD1081 Datasheet(HTML) 70 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

Datasheet Download

Link URL