ADPD1081 datasheet(64/74 Pages) AD

64 / 74 page

ADPD1080/ADPD1081

Data Sheet

Rev. C | Page 64 of 74

Address

Data Bit

Default

Value

Access

Name

Description

[1:0]

0x0

R/W

SLOTB_TIA_GAIN

Transimpedance amplifier gain for Time Slot B. When SLOTB_TIA_

IND_EN is enabled, this value is for Time Slot B, Channel 1 TIA gain.

When SLOTB_TIA_IND_EN is disabled, it is for all four Time Slot B

channel TIA gain settings.

0: 200 kΩ.

1: 100 kΩ.

2: 50 kΩ.

3: 25 kΩ.

0x45

[15:0]

0xADA5

R/W

SLOTB_AFE_CFG

AFE connection in Time Slot B.

0xADA5: analog full path mode (TIA_BPF_INT_ADC).

0xAE65: TIA ADC mode (must set Register 0x44, Bit 7 = 1 and

0xB065: TIA ADC mode (if Register 0x44, Bit 7 = 0).

Others: reserved.

FLOAT MODE REGISTERS

Table 41. Float Mode Registers

Address

Data Bit

Default

Value

Access

Name

Description

0x04

[15:8]

0x0

Reserved

Not applicable.

[7:4]

0x0

BG_STATUS_B

Status of comparison between background light level and

background threshold value for Time Slot B (BG_THRESH_B). A 1

in any bit location means the threshold has been crossed

BG_COUNT_B number of times. This register is cleared after it is read.

Bit 4: Time Slot B, Channel 1 exceeded threshold count.

Bit 5: Time Slot B, Channel 2 exceeded threshold count.

Bit 6: Time Slot B, Channel 3 exceeded threshold count.

Bit 7: Time Slot B, Channel 4 exceeded threshold count.

[3:0]

0x0

BG_STATUS_A

Status of comparison between background light level and

background threshold value for Time Slot A (BG_THRESH_A).

A 1 in any bit location means the threshold has been crossed

BG_COUNT_A number of times. This register is cleared once it is

read.

Bit 0: Time Slot A, Channel 1 exceeded threshold count.

Bit 1: Time Slot A, Channel 2 exceeded threshold count.

Bit 2: Time Slot A, Channel 3 exceeded threshold count.

Bit 3: Time Slot A, Channel 4 exceeded threshold count.

0x16

[15:14]

0x0

R/W

BG_COUNT_A

For Time Slot A, this is the number of times the ADC value

exceeds the BG_THRESH_A value during the float mode subtract

cycles before the BG_STATUS_A bit is set.

0: never set BG_STATUS_A.

1: set when BG_THRESH_A is exceeded 1 time.

2: set when BG_THRESH_A is exceeded 4 times.

3: set when BG_THRESH_A is exceeded 16 times.

[13:0]

0x0

R/W

BG_THRESH_A

The background threshold for Time Slot A that is compared

against the ADC result during the subtract cycles during float

mode. If the ADC result exceeds the value in this register,

BG_COUNT_A is incremented.

0x1C

[15:14]

0x0

R/W

BG_COUNT_B

For Time Slot B, this is the number of times the ADC value

exceeds the BG_THRESH_B value during the float mode subtract

cycles before the BG_STATUS_B bit is set.

0: never set BG_STATUS_B.

1: set when BG_THRESH_B is exceeded 1 time.

2: set when BG_THRESH_B is exceeded 4 times.

3: set when BG_THRESH_B is exceeded 16 times.

ADPD1081 Datasheet(PDF) 64 Page - Analog Devices

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