ADF4372 datasheet(32/47 Pages) AD

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ADF4372

Data Sheet

Rev. 0 | Page 32 of 47

Address: 0x1F, Default: 0x01, Name: REG001F

5-Bit R Counter.

[7:5] RESERVED

[4:0] R_WORD (R/W)

Table 29. Bit Descriptions for REG001F

Bit(s)

Bit Name

Description

Default

Access

[7:5]

RESERVED

Reserved.

0x0

[4:0]

R_WORD

5-Bit R Counter. b'00000 corresponds to

divide by 32.

0x1

R/W

Address: 0x20, Default: 0x14, Name: REG0020

Mux Out.

Mux Out Enable.

Mux Out Level Select.

[7:4] MUXOUT (R/W)

[1:0] RESERVED

[3] MUXOUT_EN (R/W)

[2] LEV_SEL (R/W)

Table 30. Bit Descriptions for REG0020

Bit(s)

Bit Name

Description

Default

Access

[7:4]

MUXOUT

Mux Out. This bit is used to set the mux out signal when MUXOUT_EN = 1.

0x1

R/W

0: tristate, high impedance output (only works when MUXOUT_EN = 0).

1: digital lock detect.

10: charge pump up.

11: charge pump down.

100: RDIV2.

101: N divider output.

110: VCO test modes.

111: reserved.

1000: high.

1001: VCO calibration R band/2.

1010: VCO calibration N band/2.

MUXOUT_EN

Mux Out Enable. Set to 0 if using the SDIO pin for register readback.

0x0

R/W

0: data pin used for readback.

1: mux out pin used for readback.

LEV_SEL

Mux Out Level Select. Select the voltage level of the logic at the mux out.

0x1

R/W

0: 1.8 V logic.

1: 3.3 V logic.

[1:0]

RESERVED

Reserved.

0x0

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