ADF4372 datasheet(34/47 Pages) AD

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ADF4372

Data Sheet

Rev. 0 | Page 34 of 47

Address: 0x24, Default: 0x80, Name: REG0024

Feedback.

Divis ion Selection.

[7] FB_SEL (R/W)

[3:0] RESERVED

[6:4] DIV_SEL (R/W)

Table 33. Bit Descriptions for REG0024

Bit(s)

Bit Name

Description

Default

Access

FB_SEL

Feedback.

0x1

R/W

0: divider feedback to N counter.

1: fundamental feedback to N counter.

[6:4]

DIV_SEL

Division Selection.

0x0

R/W

0: divide 1.

1: divide 2.

10: divide 4.

11: divide 8.

100: divide 16.

101: divide 32.

110: divide 64.

111: reserved.

[3:0]

RESERVED

Reserved.

0x0

Address: 0x25, Default: 0x07, Name: REG0025

Mute to Lock Detect.

Select Output Power Level.

RFOUT Enable.

Select if DIV_SEL is Double Buffered.

Doubler Path Enable.

Not Us ed.

[7] MUTE_LD (R/W)

[1:0] RF_OUT_POWER (R/W)

[6] RESERVED

[2] RF_EN (R/W)

[5] RF_DIVSEL_DB (R/W)

[3] X2_EN (R/W)

[4] X4_EN (R/W)

Table 34. Bit Descriptions for REG0025

Bit(s)

Bit Name

Description

Default

Access

MUTE_LD

Mute to Lock Detect.

0x0

R/W

0: mute to lock detect disabled.

1: mute to lock detect enabled, RF output stage gated by digital lock detect asserting

logic high.

RESERVED

Reserved.

0x0

RF_DIVSEL_DB

Select if DIV_SEL is Double Buffered.

0x0

R/W

X4_EN

Not Used.

0x0

R/W

X2_EN

Doubler Path Enable.

0x0

R/W

0: RF doubler off.

1: RF doubler on.

RF_EN

OUT Enable.

0x1

R/W

0: RF

OUT disabled.

1: RF

OUT enabled.

[1:0]

RF_OUT_POWER

Select Output Power Level.

0x3

R/W

0: −4 dBm.

1: −1 dBm.

10: 2 dBm.

11: 5 dBm.

ADF4372 Datasheet(PDF) 34 Page - Analog Devices

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