ADF4372 datasheet(16/47 Pages) AD

16 / 47 page

ADF4372

Data Sheet

Rev. 0 | Page 16 of 47

105

–96

–87

–100

–102

–104

–106

–108

–110

–6

–2

–4

REFERENCE POWER (dBm)

PHASE NOISE AT 1kHz

1kHz TO 100MHz

12kHz TO 20MHz

PHASE NOISE AT 10kHz

Figure 28. Jitter and Phase Noise, fPFD =100MHz

REFERENCE DOUBLER AND REFERENCE DIVIDER

The on-chip reference doubler allows the input reference signal

to be doubled. The doubler is useful for increasing the PFD

comparison frequency. To improve the noise performance of

the system, increase the PFD frequency. Doubling the PFD

frequency typically improves noise performance by 3 dB.

The reference divide by 2 divides the reference signal by 2,

resulting in a 50% duty cycle PFD frequency.

SPURIOUS OPTIMIZATION AND FAST LOCK

Narrow loop bandwidths can filter unwanted spurious signals.

However, these bandwidths typically have a long lock time. A

wider loop bandwidth achieves faster lock times, but can lead

to increased spurious signals inside the loop bandwidth.

OPTIMIZING JITTER

For lowest jitter applications, use the highest possible PFD

frequency to minimize the contribution of inband noise from the

PLL. Set the PLL filter bandwidth such that the inband noise of the

PLL intersects with the open-loop noise of the VCO, minimizing

the contribution of both to the overall noise.

Use the ADIsimPLL design tool for this task.

Additional Optimization on Loop Filter

The PLL filter is designed to find an optimum bandwidth for

the reference, PFD, and VCO noise, depending on the system

requirements. In addition to this design, when the Σ-Δ modulator

(SDM) is enabled, further optimization may be necessary to filter

SDM noise.

Reducing Σ-Δ Modulator Noise

In fractional mode, SDM noise becomes apparent and starts

to contribute to overall phase noise. This noise can be reduced

to insignificant levels by using a series resistor between the

CPOUT pin and the loop filter. Place this resistor close to the

CPOUT pin. A reasonable resistor value does not affect the loop

bandwidth and phase margin of the designed loop filter. In most

cases, 91 Ω gives the best results. This resistor is not required in

integer mode (SDM not enabled) or when a narrow-band loop

filter is used (SDM noise attenuated).

SPUR MECHANISMS

This section describes the two different spur mechanisms that

arise with a fractional-N synthesizer and how to minimize them

in the ADF4372.

Integer Boundary Spurs

One mechanism for fractional spur creation is the interactions

between the RF VCO frequency and the reference frequency.

When these frequencies are not integer related (which is the

purpose of a fractional-N synthesizer), spur sidebands appear on

the VCO output spectrum at an offset frequency that corresponds

to the beat note or the difference in frequency between an integer

multiple of the reference and the VCO frequency. These spurs

are attenuated by the loop filter and are more noticeable on

channels close to integer multiples of the reference where

the difference frequency can be inside the loop bandwidth.

Reference Spurs

Reference spurs are generally not a problem in fractional-N

synthesizers because the reference offset is far outside the loop

bandwidth. However, any reference feedthrough mechanism

that bypasses the loop can cause a problem. Feedthrough of low

levels of on-chip reference switching noise through the prescaler

back to the VCO can result in reference spur levels as high as

−100 dBc.

LOCK TIME

The PLL lock time divides into a number of settings. The total lock

time for changing frequencies is the sum of the four separate times:

synthesizer lock, VCO band selection, automatic level calibration

(ALC), and PLL settling time.

Synthesizer Lock

The synthesizer lock timeout ensures that the VCO calibration

DAC, which forces the VCO tune voltage (VTUNE), has settled

to a steady value for the band select circuitry. The SYNTH_LOCK_

TIMEOUT bit and the TIMEOUT bits select the length of time

the DAC is allowed to settle to the final voltage before the VCO

calibration process continues to the next phase (VCO band

selection).

The PFD frequency is the clock for this logic, and the duration

is set using the following equation:

1024

PFD

SYNTH LOCK TIMEEOUT

TIMEOUT

×+

(13)

where:

SYNTH_LOCK_TIMEOUT is programmed in Address 0x33.

TIMEOUT is programmed in Address 0x31 and Address 0x32.

The calculated time must be greater than or equal to 20 µs.

For the SYNTH_LOCK_TIMEOUT bit, the minimum value is

2 and the maximum value is 31. For the TIMEOUT bits, the

minimum value is 2 and the maximum value is 1023.

ADF4372 Datasheet(PDF) 16 Page - Analog Devices

ADF4372 Datasheet(HTML) 16 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Datasheet Download

Link URL