ADF4372 datasheet(41/47 Pages) AD

41 / 47 page

Data Sheet

ADF4372

Rev. 0 | Page 41 of 47

Address: 0x35, Default: 0x4C, Name: REG0035

ADC Clock Divider.

[7:0] ADC_CLK_DIVIDER (R/W)

Table 49. Bit Descriptions for REG0035

Bit(s)

Bit Name

Description

Default

Access

[7:0]

ADC_CLK_DIVIDER

ADC Clock Divider. ADC_CLK = f

PFD/((ADC_CLK_DIV × 4) + 2).

0x4C

R/W

Address: 0x36, Default: 0x30, Name: REG0036

Res erved.

[7:0] ICP_ADJUST_OFFSET (R/W)

Table 50. Bit Descriptions for REG0036

Bit(s)

Bit Name

Description

Default

Access

[7:0]

ICP_ADJUST_OFFSET

Reserved.

0x30

R/W

Address: 0x37, Default: 0x00, Name: REG0037

Selects Band in Core when Tes t Mode

is Enabled.

[7:0] SI_BAND_SEL (R/W)

Table 51. Bit Descriptions for REG0037

Bit(s)

Bit Name

Description

Default

Access

[7:0]

SI_BAND_SEL

Selects Band in Core when Test Mode is Enabled.

0x0

R/W

Address: 0x38, Default: 0x00, Name: REG0038

Selects Core when Tes t Mode is

Enabled.

Sets VCO Bias when Tes t Mode is

Enabled.

[7:4] SI_VCO_SEL (R/W)

[3:0] SI_VCO_BIAS_CODE (R/W)

Table 52. Bit Descriptions for REG0038

Bit(s)

Bit Name

Description

Default

Access

[7:4]

SI_VCO_SEL

Selects Core when Test Mode is Enabled.

0x0

R/W

0: all cores off.

1: VCO Core D.

10: VCO Core C.

100: VCO Core B.

1000: VCO Core A.

[3:0]

SI_VCO_BIAS_CODE

Sets VCO Bias when Test Mode is Enabled.

0x0

R/W

0000: maximum VCO bias (approximately 3.2 V).

1111: minimum VCO bias (approximately 1.8 V).

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