ADF4372 datasheet(6/47 Pages) AD

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ADF4372

Data Sheet

Rev. 0 | Page 6 of 47

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

FREQUENCY LOCK TIME7

Lock Time with Automatic Calibration

Bypassed

µs

1 T

A = 25°C, AVDD = 3.3 V, VCC_VCO = 5.0 V, prescaler = 4/5, reference frequency (fREFP) = 50 MHz, fPFD = 50 MHz, and RF frequency (fRF) = 5001 MHz. RF8x enabled. All RF

outputs are disabled.

2 Guaranteed by design and characterization.

3 RF output power using the EV-ADF4372SD2Z differential outputs combined using a Marki BAL-0036 balun, and measured by a spectrum analyzer with the evaluation

board and cable losses de-embedded. Highest power output selected for RF8P, RF8N, RFAUX8P, and RFAUX8N.

4 Use this value to calculate the phase noise for any application. To calculate inband phase noise performance as seen at the VCO output, use the following formula: −233 +

10log(fPFD) + 20logN. The result is the lowest noise mode for the fractional channel.

5 Use this value to calculate the phase noise for any application. To calculate inband phase noise performance as seen at the VCO output, use the following formula: −234 +

10log(fPFD) + 20logN. The result is the lowest noise mode for the integer channel.

6 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at a radio frequency

(fRF) and at a frequency offset (fOFFSET) is given by PN1_f + 10log(10 kHz/fOFFSET) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in

the ADIsimPLL design tool.

7 Lock time is measured for 100 MHz jump with standard evaluation board configuration.

TIMING SPECIFICATIONS

Table 2.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

Serial Port Interface (SPI) Timing

See Figure 2, Figure 3, and Figure 4

SCLK Frequency

SCLK

MHz

SCLK Period

SCLK

SCLK Pulse Width High

HIGH

SCLK Pulse Width Low

LOW

SDIO Setup Time

SDIO Hold Time

SCLK Falling Edge to SDIO Valid Propagation

Delay

ACCESS

CS Rising Edge to SDIO High-Z

CS Fall to SCLK Rise Setup Time

SCLK Rise to CS Rise Hold Time

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