ADF4372 datasheet(40/47 Pages) AD

40 / 47 page

ADF4372

Data Sheet

Rev. 0 | Page 40 of 47

Address: 0x32, Default: 0x04, Name: REG0032

ADC Mux Select.

Us ed as Part of the ALC Wait Tim e

and Synthetic Lock Tim e.

ADC Enable.

ADC Fas t Convers ion.

Enables ADC Convers ion.

ADC Continuous Convers ion.

[7] ADC_MUX_SEL (R/W)

[1:0] TIMEOUT[9:8] (R/W)

[6] RESERVED

[2] ADC_ENABLE (R/W)

[5] ADC_FAST_CONV (R/W)

[3] ADC_CONVERSION (R/W)

[4] ADC_CTS_CONV (R/W)

Table 46. Bit Descriptions for REG0032

Bit(s)

Bit Name

Description

Default

Access

ADC_MUX_SEL

Analog-to-Digital Converter (ADC) Mux Select.

0x0

R/W

0: proportional to absolute temperature (PTAT) voltage muxed to ADC input.

1: scaled VTUNE voltage muxed to ADC input.

RESERVED

Reserved.

0x0

ADC_FAST_CONV

ADC Fast Conversion.

0x0

R/W

0: disabled.

1: enabled.

ADC_CTS_CONV

ADC Continuous Conversion.

0x0

R/W

0: disabled.

1: enabled.

ADC_CONVERSION

Enables ADC Conversion.

0x0

R/W

0: no ADC conversion.

1: performs ADC conversion.

ADC_ENABLE

ADC Enable.

0x1

R/W

0: disabled.

1: enabled.

[1:0]

TIMEOUT[9:8]

Used as Part of the ALC Wait Time and Synthetic Lock Time. See the Lock Time section

for details.

0x0

R/W

Address: 0x33, Default: 0x0C, Name: REG0033

Part of VCO Calibration Routine.

[7:5] RESERVED

[4:0] SYNTH_LOCK_TIMEOUT (R/W)

Table 47. Bit Descriptions for REG0033

Bit(s)

Bit Name

Description

Default

Access

[7:5]

RESERVED

Reserved.

0x0

[4:0]

SYNTH_LOCK_TIMEOUT

Part of VCO Calibration Routine. See the Lock Time section for details.

0xC

R/W

Address: 0x34, Default: 0x9E, Name: REG0034

Res erved.

Wait Tim e for ALC Loop to Settle.

[7:5] VCO_FSM_TEST_MODES (R/W)

[4:0] VCO_ALC_TIMEOUT (R/W)

Table 48. Bit Descriptions for REG0034

Bit(s)

Bit Name

Description

Default

Access

[7:5]

VCO_FSM_TEST_MODES

Reserved.

0x4

R/W

[4:0]

VCO_ALC_TIMEOUT

Wait Time for ALC Loop to Settle. See the Lock Time section for details.

0x1E

R/W

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