ADF4372 datasheet(10/47 Pages) AD

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ADF4372

Data Sheet

Rev. 0 | Page 10 of 47

Pin No.

Mnemonic

Description

VCC_MUX

Power Supply for the VCO Mux. The voltage on this pin must have the same value as AV

DD.

VCC_3V

Analog Power Supply. The voltage on this pin must have the same value as AV

DD.

VDD_NDIV

N Divider Power Supply. The voltage on this pin must have the same value as AV

DD.

VDD_LS

Level Shifter Power Supply. The voltage on this pin must have the same value as AV

DD.

Chip Select, CMOS Input. When CS goes high, the data stored in the shift register is loaded into the

SDIO

Serial Data Input Output. This input is a high impedance CMOS input.

SCLK

Serial Clock Input. Data is clocked into the 24-bit shift register on the clock rising (or falling) edge. This

input is a high impedance CMOS input.

VCC_LDO_3V

Regulator Input for 1.8 V Digital Logic. The voltage on this pin must have the same value as AV

DD.

Chip Enable. Connect to 3.3 V or AV

DD.

TEST

Factory Test Pin. Connect this pin to ground.

MUXOUT

Mux Output. The mux output allows the digital lock detect, the analog lock detect, scaled RF, or the

scaled reference frequency to be externally accessible. This pin can be programmed to output the

REFP

Reference Input. If driving the device with a single-ended reference, ac couple the signal to the REFP

pin.

REFN

Complementary Reference Input. If unused, ac couple this pin to GND. REFP and REFN must be ac-

coupled if driven differentially. If driven single-ended, the reference signal must be connected to REFP,

and the REFN must be ac-coupled to GND. In differential configuration, the differential impedance is

100 Ω.

VCC_REF

Power Supply to the Reference Buffer. The voltage on this pin must have the same value as AV

DD.

VDD_PFD

Power Supply to the Phase Frequency Detector (PFD). The voltage on this pin must have the same

value as AV

DD.

VDD_VP

Charge Pump Power Supply. The voltage on this pin must have the same value as AV

DD. A 1 μF

decoupling capacitor to GND must be included to minimize spurious signals.

Exposed Pad. The land grid array (LGA) has an exposed pad that must be soldered to a metal plate on

the PCB for mechanical reasons and to the GND.

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