SH7705 datasheet(86/739 Pages) RENESAS

86 / 739 page

Rev. 2.00, 09/03, page 40 of 690

2.5

Features of CPU Core Instructions

2.5.1

Instruction Execution Method

Instruction Length: All instructions have a fixed lengthof 16bits and are executedinthe

sequential pipeline. In the sequential pipeline, almost all instructions can be executed in one cycle.

All data items are handles in longword (32 bits). Memory can be accessed in byte, word, or

longword. In this case, Memory byte or word data is sign-extended and operated on as longword

data. Immediate data is sign-extended to longword size for arithmetic operations (MOV, ADD,

and CMP/EQ instructions) or zero-extended to longword size for logical operations (TST, AND,

OR, and XOR instructions).

Load/Store Architecture: Basic operations are executed between registers. In operations

involving memory, data is first loaded into a register (load/store architecture). However, bit

manipulation instructions such as AND are executed directly on memory.

Delayed Branching: Unconditional branch instructions are executed as delayed branches. With a

delayed branch instruction, the branch is made after execution of the instruction (called the slot

instruction) immediately following the delayed branch instruction. This minimizes disruption of

the pipeline when a branch is made.

This LSI supports two types of conditional branch instructions: delayed branch instruction or

normal branch instruction.

Example:

BRA

TARGET

ADD

R1, R0

; ADD is executed before branching to the TARGET

TBit: The result of a comparison is indicated by the T bit in the status register (SR), and a

conditional branch is performed according to whether the result is True or False. Processing speed

has been improved by keeping the number of instructions that modify the T bit to a minimum.

Example:

ADD

#1, R0

; The T bit cannot be modified by the ADD instruction

CMP/EQ

#0, R0

;The T bit is setto 1 if R0 is 0.

Target

; Branch to TARGET if the T bit is set to 1 (R0=0).

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