SLG47503 datasheet(101/191 Pages) DIALOG

101 / 191 page

Datasheet

16-Jul-2021

CFR0011-120-00

Revision 2.0

101 of 191

SLG47502/03

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Preliminary

down.

 registers [1483:1482], [1487:1486] = 01 – one-DFF synchronization by clock falling edge. When Oscillator Power-down signal

comes, Oscillator generates full output pulse and then stops.

 registers [1483:1482], [1487:1486] = 10 or 11 – without synchronization (asynchronous reset). When Oscillator Power-down

signal comes, Oscillator output goes low immediately.

If I2C is used to change the synchronization mode there will be a pulse at the Oscillator output when the synchronization mode

is changed from 10 or 11 (asynchronous reset).

13.2 OSCILLATOR0 (2.048 KHZ)

Note: It's highly recommended to use OSC0 without the startup delay (register[1484] = 1).

Figure 86: Oscillator0 Block Diagram

/12

/24

/64

registers [1466:1464]

registers [1470:1468]

Second Stage

Divider

to Connection Matrix

Input [57]

to Connection Matrix

Input [58]

OUT1

OUT0

2.048 kHz Pre-divider Clock

DIV /1 /2 /4 /8

registers [1454:1453]

to CNT/DLYs Clock Scheme

Ext. CLK Sel register [1448]

OSC0

(2.048 kHz)

OUT

PWR DOWN/

FORCE O N

Ext. Clock

PWR DOWN/Force On

Matrix Output control register [1449]

Force Power On

Auto Power On

from Connection Matrix

Output [96]

OSC Power Mode

OSC0 matrix out 1 enable reg [1452]

OSC0 matrix out0 enable reg [1451]

Predivider

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