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SLG47503 Datasheet(PDF) 102 Page - Dialog Semiconductor |
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SLG47503 Datasheet(HTML) 102 Page - Dialog Semiconductor |
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102 / 191 page ![]() Datasheet 16-Jul-2021 CFR0011-120-00 Revision 2.0 102 of 191 © 2021 Dialog Semiconductor SLG47502/03 Low Voltage GreenPAK Programmable Mixed-Signal Matrix Preliminary 13.3 OSCILLATOR1 (25 MHZ) Figure 87: Oscillator1 Block Diagram /2 /3 /4 /8 /12 /24 /64 0 1 2 3 4 5 6 7 registers [1474:1472] to Connection Matrix Input [59] 25 MHz Pre-divider Clock DIV /1 /2 /4 /8 / 12 /24 /48 /96 registers [1462:1460] to CNT/DLYs Clock Scheme Ext. CLK Sel register [1456] OSC1 (25 MHz) OUT PWR DOWN/ FORC E O N 0 1 Ext. Clock PWR DOWN/Force On Matrix Output control register [1457] Force Power On Auto Power On 0 1 from Connection Matrix Output [97] OSC Power Mode register [1458] OSC1 matrix out enable reg [1459] Startup delay register [1480] Predivider Second Stage Divider |
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