SLG47503 datasheet(103/191 Pages) DIALOG

103 / 191 page

Datasheet

16-Jul-2021

CFR0011-120-00

Revision 2.0

103 of 191

SLG47502/03

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Preliminary

13.4 CNT/DLY CLOCK SCHEME

Each CNT/DLY within Multi-Function macrocell has its own additional clock divider connected to oscillators pre-divider. Available

dividers are:

 OSC0/1, OSC0/8, OSC0/64, OSC0/512, OSC0/4096, OSC0/32768, OSC0/262144

 OSC1/1, OSC1/4, OSC1/8, OSC1/64, OSC1/512

13.5 EXTERNAL CLOCKING

The SLG47502/03 supports several ways to use an external, higher accuracy clock as a reference source for internal operations.

13.5.1 GPIO Source for Oscillator0 (2.048 kHz)

When register [1448] is set to 1, an external clocking signal on GPIOx will be routed in place of the internal oscillator derived

2.048 kHz clock source. See Figure 86. The low and high limits for external frequency that can be selected are 0 MHz and 10 MHz.

13.5.2 GPIO Source for Oscillator1 (25 MHz)

When register [1456] is set to 1, an external clocking signal on GPIOx will be routed in place of the internal oscillator derived

25 MHz clock source. See Figure 87. The external frequency range is 0 MHz to 20 MHz at VDD = 1.1 V, 30 MHz at VDD = 1.2 V,

50 MHz at VDD = 1.3 V.

Figure 88: Clock Scheme

/64

/512

/64

/512

/4096

/32768

/262144

from 25 MHz Pre-divided clock

from 2.048 kHz Pre-divided clock

CNT (x-1) overflow

from Connection Matrix out

(separate for each CNT/DLY macrocell)

reserved

CNT/DLY/

ONESHOT/

FREQ_DET/

DLY_EDGE_DET

CNT overflow

CNT0/CNT1/CNT2/CNT3/

CNT4/CNT5/CNT6/CNT7

registers [3:0]

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