SLG47503 datasheet(110/191 Pages) DIALOG

110 / 191 page

Datasheet

16-Jul-2021

CFR0011-120-00

Revision 2.0

110 of 191

SLG47502/03

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Preliminary

Next, only LUTs are configured. Next, all other macrocells are initialized. After macrocells are initialized, internal POR matrix

signal switches from LOW to HIGH. The last are output pins that become active and determined by the input signals.

14.3.1 Initialization

All internal macrocells by default have initial low level. Starting from indicated power-up time of 0.811 V to 1.078 V, macrocells in

SLG47502/03 are powered on while forced to the reset state. All outputs are in Hi-Z and chip starts loading data from NVM. Then

the reset signal is released for internal macrocells and they start to initialize according to the following sequence:

Input pins, ACMP, Pull-up/down.

LUTs.

DFFs, Delays/Counters.

POR output to matrix.

Output pin corresponds to the internal logic.

The Vref output pin driving signal can precede POR output signal going high by 3

µs to 5 µs. The POR signal going high indicates

the mentioned power-up sequence is complete.

Note: The maximum voltage applied to any pin should not be higher than the VDD level. There are ESD Diodes between pin

→VDD and pin → GND on each pin. So, if the input signal applied to pin is higher than VDD, then current will sink through the

diode to VDD. Exceeding VDD results in leakage current on the input pin, and VDD will be pulled up, following the voltage on the

input pin.There is no effect from input pin when input voltage is applied at the same time as VDD.

Figure 96: Internal Macrocell States During POR Sequence

Unpredictable

VDD

Input PIN _out

to matrix

LUT/FILTER_out

to matrix

Programmable Delay_out

to matrix

DFF/LATCH/ACMP/

Edge Detector in

Filter_out to matrix

Delay_out

to matrix

POR_out

to matrix

Ext. GPO

VDD _out

to matrix

Determined by Input signals

Starts to detect input edges

Determined by Input signals

Starts to detect input edges

Determined by input signals

Determined by External Signal

Guaranteed HIGH before POR_GPI

Determined by input signals

OUT = IN without Delay

Determined by initial state

Determined by input signals

OUT = IN without Delay

Tri-state

Output State Unpredictable

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