SLG47503 datasheet(113/191 Pages) DIALOG

113 / 191 page

Datasheet

16-Jul-2021

CFR0011-120-00

Revision 2.0

113 of 191

SLG47502/03

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Preliminary

15.3 I2C SERIAL GENERAL TIMING

General timing characteristics for the I2C Serial Communications macrocell are shown in Figure 99. Timing specifications can be

found in the AC Characteristics section.

15.4 I2C SERIAL COMMUNICATIONS COMMANDS

15.4.1 Byte Write Command

Following the Start condition from the Master, the Control Code [4 bits], the Block Address [3 bits], and the R/W bit (set to “0”),

are placed onto the I2C bus by the Master. After the SLG47502/03 sends an Acknowledge bit (ACK), the next byte transmitted

by the Master is the Word Address. The Block Address (A10, A9, A8), combined with the Word Address (A7 through A0), together

set the internal address pointer in the SLG47502/03, where the data byte is to be written. After the SLG47502/03 sends another

Acknowledge bit, the Master will transmit the data byte to be written into the addressed memory location. The SLG47502/03 again

provides an Acknowledge bit and then the Master generates a Stop condition. The internal write cycle for the data will take place

at the time that the SLG47502/03 generates the Acknowledge bit.

It is possible to latch all IOs during I2C write command, register [1425] = 1 - Enable. It means that IOs will remain their state until

the write command is done.

Figure 98: Basic Command Structure

Figure 99: I2C General Timing Characteristics

R/W

Control Byte

Word Address

Control

Code

Block

Address

Read/Write bit

(1 = Read, 0 = Write)

ACK

Acknowledge

bit

Start

bit

Not used, set to 0

SCL

tSU_STO

tBUF

tHIGH

tLOW

tSU_DAT

tHD_DAT

tHD_STA

tSU_STA

tVD_ACK

tVD_DAT

SDA IN

SDA OUT

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